公开(公告)号：US09666518B1

公开(公告)日：2017-05-30

申请号：US15420410

申请日：2017-01-31

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko Funatsu ,  Yukihiro Sato ,  Takamitsu Kanazawa ,  Masahiro Koido ,  Hiroyoshi Taya

IPC: H01L23/498 ,  H01L25/07 ,  H01L23/053 ,  H01L23/10 ,  H01L23/00 ,  H01L21/52 ,  H01L21/54 ,  H01L23/16 ,  H01L29/417 ,  H01L23/04 ,  H01L23/02 ,  H01L23/057 ,  H02S40/32

CPC classification number: H01L23/49838 ,  H01L21/52 ,  H01L21/54 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/12 ,  H01L23/15 ,  H01L23/16 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/071 ,  H01L25/072 ,  H01L29/41708 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H02S40/32 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2224/85399

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

公开(公告)号：US09396971B2

公开(公告)日：2016-07-19

申请号：US14805218

申请日：2015-07-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro Sato ,  Nobuya Koike

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/58 ,  H01L23/31 ,  H01L23/00 ,  H01L23/433 ,  H01L25/065

CPC classification number: H01L21/561 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.

公开(公告)号：US20140087520A1

公开(公告)日：2014-03-27

申请号：US14037360

申请日：2013-09-25

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko Funatsu ,  Tomoaki Uno ,  Toru Ueguri ,  Yukihiro Sato

IPC: H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

Abstract translation: 为了提高将带施加到基板的后表面上的带的可靠性，同时确保施加到基板的后表面的带的耐热性。 在支撑构件中设置的沟槽的底表面和驱动器IC芯片的上表面之间存在间隙。 另一方面，引线框架的上表面侧由支撑构件支撑，使得沟槽的底表面接触安装在低MOS芯片上的低MOS片的上表面。 因此，即使在驱动IC芯片和Low-MOS芯片安装在引线框架的上表面侧的状态下，也可以将带子可靠地施加到引线框架的后表面（特别是后端） 产品区域的表面）。

公开(公告)号：US09887151B2

公开(公告)日：2018-02-06

申请号：US15174568

申请日：2016-06-06

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro Sato ,  Akira Muto ,  Ryo Kanda ,  Takamitsu Kanazawa

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L29/739 ,  H01L27/06 ,  H01L25/075 ,  H02P27/06

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L25/0753 ,  H01L27/0664 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4903 ,  H01L2224/49111 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

公开(公告)号：US09530723B2

公开(公告)日：2016-12-27

申请号：US14862102

申请日：2015-09-22

Applicant: Renesas Electronics Corporation

Inventor： Akira Muto ,  Koji Bando ,  Yukihiro Sato ,  Kazuhiro Mitamura

IPC: H01L23/495 ,  H01L23/00 ,  B60L3/00 ,  B60L11/18 ,  B60L15/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/544

CPC classification number: H01L23/49575 ,  B60L3/003 ,  B60L11/1803 ,  B60L15/007 ,  B60L2220/12 ,  B60L2240/525 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49565 ,  H01L23/544 ,  H01L23/564 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/29116 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40998 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/77704 ,  H01L2224/78704 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/84136 ,  H01L2224/84138 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/84862 ,  H01L2224/8585 ,  H01L2224/92147 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  Y02T10/645 ,  Y02T10/7005 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/05559 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.

Abstract translation: 假设在引线框架中设置一对悬挂部件，并且夹子包括主体部分和一对延伸部分，所述一对延伸部分被安装并支撑在所述一对悬挂部分上。 因此，夹子安装在一个引线（一点）上，一对悬挂部分（两点）和夹子被三个点支撑。

公开(公告)号：US09142479B2

公开(公告)日：2015-09-22

申请号：US13973077

申请日：2013-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenya Kawano ,  Hiroyuki Nakamura ,  Yukihiro Sato

IPC: H01L23/373 ,  H01L29/772 ,  H01L29/78 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/373 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L29/772 ,  H01L29/7813 ,  H01L2224/05553 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.

Abstract translation: 提供一种具有半导体器件和安装板的电子器件。 半导体器件具有管芯焊盘，管芯焊盘上的半导体芯片，将管芯焊盘连接到半导体芯片的耦合部件以及覆盖半导体芯片的上部和管芯焊盘侧表面的半导体封装件。 在该半导体器件中，将安装板耦合到管芯焊盘的耦合部件的平面面积小于从半导体封装材料露出的裸片焊盘的下表面的平面面积。 这使得可以减少由于存在于管芯焊盘和半导体芯片之间的耦合部件的温度循环而导致的芯片焊盘和半导体芯片之间的分离。

公开(公告)号：US20150214209A1

公开(公告)日：2015-07-30

申请号：US14685145

申请日：2015-04-13

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko Funatsu ,  Tomoaki Uno ,  Toru Ueguri ,  Yukihiro Sato

IPC: H01L25/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L21/683 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

Abstract translation: 为了提高将带施加到基板的后表面上的带的可靠性，同时确保施加到基板的后表面的带的耐热性。 在支撑构件中设置的沟槽的底表面和驱动器IC芯片的上表面之间存在间隙。 另一方面，引线框架的上表面侧由支撑构件支撑，使得沟槽的底表面接触安装在低MOS芯片上的低MOS片的上表面。 因此，即使在驱动IC芯片和Low-MOS芯片安装在引线框架的上表面侧的状态下，也可以将带子可靠地施加到引线框架（特别是后端）的后表面 产品区域的表面）。

公开(公告)号：US08564112B2

公开(公告)日：2013-10-22

申请号：US13655446

申请日：2012-10-19

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Nakamura ,  Atsushi Fujiki ,  Tatsuhiro Seki ,  Nobuya Koike ,  Yukihiro Sato ,  Kisho Ashida

IPC: H01L23/48 ,  H01L23/10

CPC classification number: H01L27/07 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/66 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.

Abstract translation: 提高半导体器件的性能和可靠性。 对于半导体芯片CP1，用于开关的功率MOSFET Q1和Q2，用于检测功率MOSFET Q1的发热的二极管DD1，用于检测功率MOSFET Q2的发热的二极管DD2和多个焊盘电极PD 。 功率MOSFET Q1和二极管DD1布置在侧面SD1侧的第一MOSFET区域RG1中，功率MOSFET Q2和二极管DD2布置在侧面SD2侧的第二MOSFET区RG2中。 二极管DD1沿着侧面SD1配置，二极管DD2沿着侧面SD2配置，除源极的焊盘电极PDS1和PDS2以外的所有焊盘电极PD沿着二极管DD1和DD2之间的侧面SD3排列。

公开(公告)号：US10515877B2

公开(公告)日：2019-12-24

申请号：US15934310

申请日：2018-03-23

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro Sato ,  Toshinori Kiyohara

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

公开(公告)号：US09704844B2

公开(公告)日：2017-07-11

申请号：US15133032

申请日：2016-04-19

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko Funatsu ,  Tomoaki Uno ,  Toru Ueguri ,  Yukihiro Sato

IPC: H01L23/495 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).