公开(公告)号：US11658131B2

公开(公告)日：2023-05-23

申请号：US17168337

申请日：2021-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Un-Byoung Kang ,  Jong Ho Lee

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/14 ,  H01L23/49816 ,  H01L24/14

Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

公开(公告)号：US11222873B2

公开(公告)日：2022-01-11

申请号：US16936882

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US10756055B2

公开(公告)日：2020-08-25

申请号：US16295276

申请日：2019-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Yungcheol Kong ,  Kyoungsei Choi

IPC: H01L25/04 ,  H01L27/146 ,  H01L23/00 ,  H01L23/49 ,  H01L23/528 ,  H01L23/48

Abstract: Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.

公开(公告)号：US10535534B2

公开(公告)日：2020-01-14

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US10177188B2

公开(公告)日：2019-01-08

申请号：US15583224

申请日：2017-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Yungcheol Kong ,  Hyunsu Jun ,  Kyoungsei Choi

IPC: H01L27/146 ,  H01L31/0203 ,  H01L23/00 ,  H01L31/024

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

公开(公告)号：US09343361B2

公开(公告)日：2016-05-17

申请号：US14072777

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L21/76 ,  H01L21/326 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

公开(公告)号：US09023716B2

公开(公告)日：2015-05-05

申请号：US14147718

申请日：2014-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chungsun Lee ,  Jung-Seok Ahn ,  Kwang-chul Choi ,  Un-Byoung Kang ,  Jung-Hwan Kim ,  Joonsik Sohn ,  Jeon Il Lee

IPC: H01L21/58 ,  H01L21/304 ,  H01L21/683

CPC classification number: H01L21/6835 ,  B32B37/1284 ,  B32B37/18 ,  B32B37/24 ,  B32B37/26 ,  B32B38/04 ,  B32B38/10 ,  B32B38/162 ,  B32B2037/268 ,  B32B2315/08 ,  B32B2457/14 ,  H01L21/02057 ,  H01L21/02126 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/14 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13023 ,  H01L2924/12042 ,  H01L2924/181 ,  Y10S438/977 ,  H01L2924/00

Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract translation: 一种处理衬底的方法包括：在衬底和载体之间提供接合层，以将衬底粘合到载体上，在衬底由载体支撑的同时处理衬底，以及去除结合层以使衬底与载体分离。 粘合层可以包括热固性剥离层和热固性胶层，其中至少一个热固性胶层设置在热固性剥离层的每一侧上。

公开(公告)号：US20130267057A1

公开(公告)日：2013-10-10

申请号：US13909160

申请日：2013-06-04

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC: H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘合图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。

公开(公告)号：US20130260551A1

公开(公告)日：2013-10-03

申请号：US13903164

申请日：2013-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC: H01L21/48

CPC classification number: H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

Abstract translation: 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。 有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。 由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。 此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。 这也减少了分层问题。 此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。 因此，可以实现具有增强的可靠性的半导体器件。

公开(公告)号：US12165991B2

公开(公告)日：2024-12-10

申请号：US18162878

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Un-Byoung Kang ,  Jaekyung Yoo ,  Teak Hoon Lee

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.