Patent search ap:("STATS ChipPAC Pte. Ltd.") AND inv:"Won Kyoung Choi" Page 2

11.

发明授权
Semiconductor device and method of forming microelectromechanical systems (MEMS) package 有权

公开(公告)号：US11370655B2

公开(公告)日：2022-06-28

申请号：US16825567

申请日：2020-03-20

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin , Won Kyoung Choi , Kang Chen , Ivan Micallef

IPC: B81B7/00 , B81C1/00 , H01L21/56 , H01L23/538 , H01L23/552 , H01L23/00 , H01L25/10 , H01L25/00

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

12.

发明授权
Semiconductor device and method of forming low profile fan-out package with vertical interconnection units 有权

公开(公告)号：US09978665B2

公开(公告)日：2018-05-22

申请号：US15611110

申请日：2017-06-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu , Il Kwon Shim , Yaojian Lin , Won Kyoung Choi

IPC: H01L21/00 , H01L23/48 , H01L23/00 , H01L23/498 , H01L25/065 , H01L21/56 , H01L23/538

CPC classification number: H01L23/481 , H01L21/568 , H01L23/49833 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/94 , H01L24/96 , H01L25/0657 , H01L2224/03 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/73204 , H01L2224/73267 , H01L2224/81191 , H01L2224/81192 , H01L2224/94 , H01L2225/06513 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/00012 , H01L2924/00

Abstract: A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias.

13.

发明申请
Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package 审中-公开

公开(公告)号：US20170297903A1

公开(公告)日：2017-10-19

申请号：US15362199

申请日：2016-11-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin , Won Kyoung Choi , Kang Chen , Ivan Micallef

IPC: B81B7/00 , B81C1/00 , H01L21/56 , H01L23/538 , H01L23/00 , H01L25/10 , H01L23/552 , H01L25/00

CPC classification number: B81B7/007 , B81C1/0023 , B81C1/00301 , B81C1/00904 , H01L21/561 , H01L21/568 , H01L23/5389 , H01L23/552 , H01L24/16 , H01L24/19 , H01L24/81 , H01L24/96 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/03 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2224/73267 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/13091 , H01L2924/15 , H01L2924/15311 , H01L2924/16251 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/11 , H01L2224/81 , H01L2924/00012 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00014 , H01L2924/014

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

14.

发明申请
Semiconductor Device and Method of Singulating Thin Semiconductor Wafer on Carrier Along Modified Region Within Non-Active Region Formed by Irradiating Energy 审中-公开

公开(公告)号：US20170092529A1

公开(公告)日：2017-03-30

申请号：US15379178

申请日：2016-12-14

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han , Il Kwon Shim , Won Kyoung Choi

IPC: H01L21/683 , H01L23/48 , H01L23/00 , H01L23/544 , H01L21/78

CPC classification number: H01L21/6836 , H01L21/6835 , H01L21/78 , H01L23/481 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2221/68354 , H01L2221/68381 , H01L2223/5446 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/1132 , H01L2224/11334 , H01L2224/1146 , H01L2224/13023 , H01L2224/13025 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81903 , H01L2224/9211 , H01L2224/94 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/01082 , H01L2924/0105 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/83851 , H01L2224/05552 , H01L2224/81805

Abstract: A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer including a plurality of semiconductor die separated by a non-active region. A plurality of bumps is formed over the semiconductor die. The semiconductor wafer is mounted to the carrier with the adhesive disposed around the plurality of bumps. Irradiated energy is applied to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die. The semiconductor wafer is singulated along the modified region by applying stress to the semiconductor wafer. The adhesive is removed from around the plurality of bumps after singulating the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die comprising through silicon vias. The modified region optionally includes a plurality of vertically stacked modified regions.

15.

发明授权
Semiconductor device and method of forming a PoP device with embedded vertical interconnect units 有权

公开(公告)号：US10446479B2

公开(公告)日：2019-10-15

申请号：US15807102

申请日：2017-11-08

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu , Yaojian Lin , Kang Chen , Yu Gu , Won Kyoung Choi

IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/538 , H01L25/10 , H01L21/683 , H01L25/065 , H01L23/13 , H01L23/14

Abstract: A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.