公开(公告)号：US06710610B1

公开(公告)日：2004-03-23

申请号：US09407838

申请日：1999-09-29

申请人： Naotaka Tanaka ,  Hiroyuki Ohta ,  Ichiro Anjoh ,  Hideo Arima ,  Akio Hasebe ,  Kenichi Yamamoto

发明人： Naotaka Tanaka ,  Hiroyuki Ohta ,  Ichiro Anjoh ,  Hideo Arima ,  Akio Hasebe ,  Kenichi Yamamoto

IPC分类号： G01R3102

CPC分类号： G01R1/0441 ,  H05K3/326

摘要： Electrode pads are formed on a tape circuit to correspond to positions of solder bumps on an IC. A plurality of pins formed on a periphery of the tape circuit provide electrical connection between the tape circuit and a mother socket. An elastomer sheet is provided between a portion of the tape circuit, on which the electrode pads are formed and the IC is mounted, and the mother socket, and a side surface of the sheet, which contacts with the tape circuit, is formed with cut grooves in lattice fashion such that respective centers of the electrode pads substantially coincide with intersections of the grooves. Thus portions defined by the grooves on the sheet are made independent from one another to enable accommodating pushing forces from the solder bumps, so that, even if dispersion in height generates between the solder bumps, the respective portions defined by the grooves are hardly influenced by one another, and so accommodate the pushing forces from the solder bumps to permit the solder bumps and the electrode pads to surely contact with each other.

摘要翻译： 电极焊盘形成在磁带电路上以对应于IC上的焊料凸块的位置。 形成在磁带电路的周边上的多个引脚在磁带电路和母插座之间提供电连接。 弹性体片材设置在带状电路的形成有电极垫的部分和安装有IC的部分之间，并且母带和与带电路接触的片材的侧表面形成有切口 凹槽以格子方式使得电极垫的各个中心基本上与凹槽的交叉重合。 因此，由片上的凹槽限定的部分彼此独立，以便能够容纳来自焊料凸块的推力，使得即使在焊料凸块之间产生高度分散，由凹槽限定的各个部分几乎不受 并且因此容纳来自焊料凸块的推力，以允许焊料凸块和电极焊盘彼此牢固地接触。

公开(公告)号：US06465876B1

公开(公告)日：2002-10-15

申请号：US08974682

申请日：1997-11-19

申请人： Makoto Kitano ,  Akihiro Yaguchi ,  Naotaka Tanaka ,  Takeshi Terasaki ,  Ichiro Anjoh ,  Ryo Haruta ,  Asao Nishimura ,  Junichi Saeki

发明人： Makoto Kitano ,  Akihiro Yaguchi ,  Naotaka Tanaka ,  Takeshi Terasaki ,  Ichiro Anjoh ,  Ryo Haruta ,  Asao Nishimura ,  Junichi Saeki

IPC分类号： H01L2302

CPC分类号： H01L23/16 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/05554 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K3/3426 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bond ed to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.

摘要翻译： 可以提高焊料凸块的连接可靠性和制造生产率的半导体器件。 在其表面上具有布线图案的绝缘带与引线框架结合。 半导体元件被加载并且电路形成的表面和半导体元件的侧面被密封树脂​​密封。 在形成各个半导体器件的布置之后，将引线框架分离成单独的金属板以形成单独的半导体器件。 这种同时生产多个半导体器件提高了生产率，并且提高了绝缘带的平坦度，从而提高了焊料凸块的连接可靠性。

公开(公告)号：US6049128A

公开(公告)日：2000-04-11

申请号：US820631

申请日：1997-03-19

申请人： Makoto Kitano ,  Ryuji Kohno ,  Naotaka Tanaka ,  Akihiro Yaguchi ,  Tetsuo Kumazawa ,  Ichiro Anjoh ,  Hideki Tanaka ,  Asao Nishimura ,  Shuji Eguchi ,  Akira Nagai ,  Mamoru Mita

发明人： Makoto Kitano ,  Ryuji Kohno ,  Naotaka Tanaka ,  Akihiro Yaguchi ,  Tetsuo Kumazawa ,  Ichiro Anjoh ,  Hideki Tanaka ,  Asao Nishimura ,  Shuji Eguchi ,  Akira Nagai ,  Mamoru Mita

IPC分类号： H01L21/60 ,  H01L23/04 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48 ,  H01L23/34 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/49572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15787

摘要： A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.

摘要翻译： 提供一种半导体器件，具有多个用于外部连接的电极的半导体芯片，除弹性体树脂形成的弹性体树脂部分，其除了多个电极中的至少一些外部结合到半导体芯片，包括树脂的带层，包括 表面上的带状布线图案，用于将印刷布线图案接合到带布线图案的多个焊料凸块，用于将半导体芯片的多个电极连接到带布线图案的引线，以及密封用于覆盖引线的树脂， 由引线连接的多个电极。 弹性体树脂的横向弹性模量不小于50MPa且不大于750MPa。

公开(公告)号：US5837567A

公开(公告)日：1998-11-17

申请号：US829230

申请日：1997-03-31

申请人： Naotaka Tanaka ,  Akihiro Yaguchi ,  Makoto Kitano ,  Tatsuya Nagata ,  Tetsuo Kumazawa ,  Atsushi Nakamura ,  Hiromichi Suzuki ,  Masayoshi Tsugane

发明人： Naotaka Tanaka ,  Akihiro Yaguchi ,  Makoto Kitano ,  Tatsuya Nagata ,  Tetsuo Kumazawa ,  Atsushi Nakamura ,  Hiromichi Suzuki ,  Masayoshi Tsugane

IPC分类号： H01L21/56 ,  H01L23/495 ,  H01L21/44

CPC分类号： H01L23/49558 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/49548 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/181

摘要： A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.

摘要翻译： 与塑料封装的半导体器件一起使用的引线框架包括其上安装有半导体芯片的突片，芯片焊盘支撑引线，与半导体芯片电耦合的内部引线，与内部引线一起形成为整体结构的外部引线 以及用于支撑芯片焊盘支撑引线和外引线的框架。 在引线框架中，仅在外引线之间设置阻挡构件。 或者，在框架和与其相邻的导线之间形成虚设外引线，以便通过坝构件将虚拟引线连接到外引线。 在组装半导体器件之后移除框架。

公开(公告)号：US5698790A

公开(公告)日：1997-12-16

申请号：US646141

申请日：1996-05-07

申请人： Asao Nishimura ,  Naotaka Tanaka ,  Isao Hirose

发明人： Asao Nishimura ,  Naotaka Tanaka ,  Isao Hirose

IPC分类号： G01N3/00 ,  G01N3/24 ,  G01N19/04

CPC分类号： G01N3/24 ,  G01N19/04 ,  G01N2203/0066 ,  G01N2203/0091

摘要： A method for measuring an adhesion strength of a resin material which is capable of accurately and readily measuring a universal adhesion strength independent of dimensions and shapes of specimen. A delamination portion is partially formed between a resin and an adherend material. Loads in two different directions are applied to an adhering interface such that opposed shear stresses are generated. As a result, a true adhering strength can be obtained from an apparent delamination propagating strength in each case.

摘要翻译： 用于测量树脂材料的粘合强度的方法，其能够准确且容易地测量与样品的尺寸和形状无关的通用粘合强度。 在树脂和被粘物之间部分形成分层部分。 将两个不同方向的载荷施加到粘附界面，从而产生相对的剪切应力。 结果，可以从每种情况下的明显的分层传播强度获得真正的粘附强度。

公开(公告)号：US20140252576A1

公开(公告)日：2014-09-11

申请号：US14354091

申请日：2011-10-31

申请人： Hisashi Tanie ,  Hiroshi Shintani ,  Naotaka Tanaka

发明人： Hisashi Tanie ,  Hiroshi Shintani ,  Naotaka Tanaka

IPC分类号： H01L23/00 ,  H01L21/52

CPC分类号： H01L23/562 ,  H01L21/52 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/488 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L2224/02123 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05011 ,  H01L2224/05016 ,  H01L2224/05023 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/05088 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11444 ,  H01L2224/1146 ,  H01L2224/13005 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27444 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29017 ,  H01L2224/2908 ,  H01L2224/30181 ,  H01L2224/32105 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/38 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40229 ,  H01L2224/4103 ,  H01L2224/41176 ,  H01L2224/73204 ,  H01L2224/8309 ,  H01L2224/83101 ,  H01L2224/8321 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2224/29155 ,  H01L2224/29147 ,  H01L2924/00012 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 μm or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.

摘要翻译： 半导体器件具有封装结构，其中半导体芯片1的顶表面通过变形吸收层2a和接合层3a电连接到导电构件4，并且其底表面通过导电构件5电连接到导电构件5 变形吸收层2b和接合层3b。 每个变形吸收层2a和2b包括布置在厚度方向中心的纳米结构层7和两层的层6和8，其间具有纳米结构层7。 纳米结构层7具有二维排列多个尺寸为1μm以下的纳米结构体9的结构，并且由于形成半导体器件的各构件的热变形差导致的热应力被 纳米结构变形9。

公开(公告)号：US08816506B2

公开(公告)日：2014-08-26

申请号：US13340165

申请日：2011-12-29

申请人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

发明人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/274 ,  H01L2224/81136 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81801 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1451 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

摘要翻译： 在层叠多个半导体芯片的半导体装置中，不会降低生产率而提高性能。 半导体器件具有多个元件，层间绝缘膜，焊盘和与依次形成在硅基板的主表面上的焊盘电连接的凸块电极，并且具有形成在硅衬底的背面上的背面电极 硅基板并与凸块电极电连接。 凸块电极具有贯穿焊盘并朝向硅衬底侧突出的突出部分。 背面电极形成为从硅衬底的背面侧朝向主面侧到达突起电极的突出部，并覆盖未到达的背面电极孔部的内侧 垫，使得背面电极与凸块电极电连接。

公开(公告)号：US08178977B2

公开(公告)日：2012-05-15

申请号：US12483751

申请日：2009-06-12

申请人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

发明人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2224/05552

摘要： When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.

摘要翻译： 当在芯片的后表面上形成通孔电极和后表面线时，由于作为通孔的一部分的后表面布线板，在芯片的后表面上形成凸部， 孔电极和后表面电线。 这导致当芯片被吸入时的空气泄漏，因此发生芯片的吸力的降低。 预先在形成背面布线衬垫和背面导线的区域中形成凹部。 后表面布线板和后表面布线设置在凹部内。 因此，通过由背面布线衬垫和后表面线的厚度引起的凸部来确保芯片的后表面的平坦度，使得当处理芯片时不会发生吸力的降低 。

公开(公告)号：US20110133336A1

公开(公告)日：2011-06-09

申请号：US13030098

申请日：2011-02-17

申请人： Naotaka Tanaka ,  Kenji Kanemitsu ,  Takafumi Kikuchi ,  Takashi Akazawa

发明人： Naotaka Tanaka ,  Kenji Kanemitsu ,  Takafumi Kikuchi ,  Takashi Akazawa

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.

摘要翻译： 一种半导体晶片，包括：在形成晶片的通孔电极的位置处形成的管状沟槽; 绝缘构件，其被埋置在所述沟槽内部和所述沟槽的上表面上; 形成在所述绝缘构件的上表面上的栅电极膜和金属膜; 形成在金属膜的上表面上的多层柱状布线孔; 以及通过多层柱状布线通孔与金属膜电连接形成的外部连接电极。 以这种方式，在薄晶片和设备开发之后，不需要具有干法蚀刻的新工艺来形成通孔电极。 此外，引入特定设计可以形成通孔电极，同时显着降低了各个工艺的难度。

公开(公告)号：US20090189256A1

公开(公告)日：2009-07-30

申请号：US12360466

申请日：2009-01-27

申请人： Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Michihiro Kawashita ,  Takahiro Naito ,  Takashi Akazawa

发明人： Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Michihiro Kawashita ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L24/16 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

摘要： After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.

摘要翻译： 在形成从其后表面侧穿过半导体衬底的环形沟槽形成并在沟槽内部和半导体衬底的后表面上形成绝缘膜之后，在绝缘膜和半导体衬底上形成通孔 从后表面侧的环形沟槽的内侧，露出在通孔的底部形成在半导体衬底的前表面上的表面保护绝缘膜。 在去除通孔底部的表面保护绝缘膜以形成露出元件表面电极的开口之后，在通孔和开口的内壁上形成连接到元件表面电极的接触电极，并且焊盘电极 由与所述接触电极相同的层形成在所述半导体衬底的后表面上。