公开(公告)号：US08779300B2

公开(公告)日：2014-07-15

申请号：US13355311

申请日：2012-01-20

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K1/11 ,  H01L29/40 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/00 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/099 ,  H05K2203/054 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post.

Abstract translation: 提供一种具有导电结构的封装基板，包括其表面上具有至少一个导电焊盘的基板主体，设置在导电焊盘上的应力缓冲金属层，应力缓冲金属层的厚度为1-20μm， 防焊层设置在基板主体上并且在其中具有至少一个开口，用于相应地暴露应力缓冲金属层的顶表面的一部分，设置在应力缓冲金属层的表面的中心部分上的金属柱，以及 焊料凸块覆盖金属柱的表面。

公开(公告)号：US08609506B2

公开(公告)日：2013-12-17

申请号：US13681152

申请日：2012-11-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuan-Yi Lin ,  Ching-Chen Hao ,  Chen Cheng Chou ,  Sheng-Yuan Lin

IPC: H01L23/36

CPC classification number: H01L23/34 ,  H01L21/4814 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract translation: 描述了具有片上散热器和成形方法的芯片的三维（3D）堆叠芯片结构。 3D堆叠芯片结构包括具有形成在前表面上的电介质层的第一基板的第一裸片。 可以在电介质层中同时形成一个或多个接合焊盘和散热器。 第一管芯与第二管芯的表面上的相应的接合焊盘接合以形成堆叠的芯片结构。 堆叠的芯片结构中产生的热可以通过散热器扩散到堆叠的芯片结构的边缘。

公开(公告)号：US08525278B2

公开(公告)日：2013-09-03

申请号：US13213863

申请日：2011-08-19

Applicant: Chia-Hua Chu ,  Chung-Hsien Lin

Inventor： Chia-Hua Chu ,  Chung-Hsien Lin

IPC: H01L27/20 ,  H01L21/98

CPC classification number: B81C1/00238 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11622 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/16145 ,  H01L2224/73257 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81054 ,  H01L2224/81065 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/8182 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.

Abstract translation: 描述了具有芯片级MEMS封装的方法和装置。 第一衬底包括MEMS器件，第二衬底包括集成电路。 第一衬底的前侧结合到第二衬底的背面。 因此，第二衬底提供了一个空腔来封装，保护或操作其中的MEMS器件。 该键可以在第一和第二衬底之间提供电连接。 在一个实施例中，穿通硅通孔用于将信号从第一衬底传送到第二衬底的前侧上的I / O连接。

公开(公告)号：US08405225B2

公开(公告)日：2013-03-26

申请号：US13437533

申请日：2012-04-02

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L21/8221 ,  H01L21/76898 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S148/164 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/013

Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Abstract translation: 半导体结构包括第一裸片，其包括第一衬底和第一衬底上的第一焊盘，第二裸片，具有与第一表面相对的第一表面和第二表面，其中第二裸片堆叠在第一裸片上， 层，其具有在第二管芯的侧壁上的垂直部分，以及在第一管芯上延伸的水平部分。

公开(公告)号：US08269354B2

公开(公告)日：2012-09-18

申请号：US12908777

申请日：2010-10-20

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/498 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

Abstract translation: 公开了一种半导体封装基板结构及其制造方法。 该结构包括具有形成在其至少一个表面上的多个电连接焊盘的基板; 多个电镀导电柱，每个覆盖相应的一个电连接焊盘和形成在该基板的表面上的绝缘保护层，并且具有用于使电镀的导电柱露出的露出部分。 本发明允许电镀导电柱之间的间隔最小化，产生集中应力和避免底部填充物的溢出，以及制造的封装的整体高度的降低。

公开(公告)号：US20120112322A1

公开(公告)日：2012-05-10

申请号：US13351144

申请日：2012-01-16

Applicant: Chuan-Yi Lin ,  Ching-Chen Hao ,  Chen Cheng Chou ,  Sheng-Yuan Lin

Inventor： Chuan-Yi Lin ,  Ching-Chen Hao ,  Chen Cheng Chou ,  Sheng-Yuan Lin

IPC: H01L29/06

CPC classification number: H01L21/76898 ,  H01L23/585 ,  H01L25/0657 ,  H01L2224/05109 ,  H01L2224/05116 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Abstract translation: 描述在半导体集成电路（IC）裸片中形成密封环。 通常在半导体IC芯片中形成通硅通孔（TSV），以便于形成三维（3D）堆叠管芯结构。 TSV可用于在3D堆叠模具结构的不同模具中的组件之间提供电连接。 密封环形成在IC管芯的金属间电介质（IMD）层中，其包围有源电路区域。 真正的环在形成TSV之前形成，防止在随后的TSV形成过程中，水分或其它不期望的化学试剂扩散到有源电路区域。

公开(公告)号：US08148826B2

公开(公告)日：2012-04-03

申请号：US13273845

申请日：2011-10-14

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/00 ,  H01L21/58 ,  H01L21/56

CPC classification number: H01L21/8221 ,  H01L21/76898 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S148/164 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/013

Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Abstract translation: 半导体结构包括第一裸片，其包括第一衬底和第一衬底上的第一焊盘，第二裸片，具有与第一表面相对的第一表面和第二表面，其中第二裸片堆叠在第一裸片上， 层，其具有在第二管芯的侧壁上的垂直部分，以及在第一管芯上延伸的水平部分。

公开(公告)号：US08053277B2

公开(公告)日：2011-11-08

申请号：US12878112

申请日：2010-09-09

Applicant: Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Hung-Jung Tu ,  Ku-Feng Yang

IPC: H01L21/50

CPC classification number: H01L21/8221 ,  H01L21/76898 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S148/164 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/013

Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.

Abstract translation: 半导体结构包括第一裸片，其包括第一衬底和第一衬底上的第一焊盘，第二裸片，具有与第一表面相对的第一表面和第二表面，其中第二裸片堆叠在第一裸片上， 层，其具有在第二管芯的侧壁上的垂直部分，以及在第一管芯上延伸的水平部分。

公开(公告)号：US07825024B2

公开(公告)日：2010-11-02

申请号：US12277829

申请日：2008-11-25

Applicant: Chuan-Yi Lin ,  Song-Bor Lee ,  Ching-Kun Huang ,  Sheng-Yuan Lin

Inventor： Chuan-Yi Lin ,  Song-Bor Lee ,  Ching-Kun Huang ,  Sheng-Yuan Lin

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/01029

Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.

Abstract translation: 提供一种形成具有穿硅通孔（TSV）的半导体器件的方法。 提供一种其上形成有第一介电层的半导体器件。 一个或多个电介质层形成在第一电介质层之上，使得每个电介质层具有层叠结构，其中一个或多个电介质层中的堆叠结构垂直对准。 堆叠结构可以是例如金属环。 然后移除堆叠结构以形成第一凹槽。 通过将第一凹部延伸到基底中形成第二凹部。 第二凹槽填充有导电材料以形成TSV。

公开(公告)号：US07811903B2

公开(公告)日：2010-10-12

申请号：US11923832

申请日：2007-10-25

Applicant: Ford B. Grigg ,  Timothy L. Jackson

Inventor： Ford B. Grigg ,  Timothy L. Jackson

IPC: H01L21/30 ,  H01L21/78 ,  H01L21/50

CPC classification number: H01L21/78 ,  H01L21/563 ,  H01L21/565 ,  H01L24/29 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/00014

Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive back side silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.

Abstract translation: 公开了用于减薄凸起的半导体晶片的方法以及用于制造非常薄型的倒装芯片的方法。 根据本发明的方法，模具化合物散布在晶片的有源面上的导电凸起之间，以在去除晶片的非活性背面硅表面的过程中和之后提供晶片结构的支撑和保护。 模具化合物还用于在随后的处理期间保持晶片的导电凸起的方面的完整性，并且在晶片被切割之后，可充当用于倒装芯片应用的底部填充材料的全部或部分。