公开(公告)号：US20120126364A1

公开(公告)日：2012-05-24

申请号：US12953624

申请日：2010-11-24

申请人： Bonnie E. Weir ,  Edward B. Harris ,  Ramnath Venkatraman

发明人： Bonnie E. Weir ,  Edward B. Harris ,  Ramnath Venkatraman

IPC分类号： H01L23/52 ,  H01L21/98

CPC分类号： H01L23/5256 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

摘要翻译： IC电容器组包括连接到一对导电迹线的多个高k金属 - 绝缘体金属（MIM）电容器。 位于一对导电迹线之一的端部上的可熔痕迹形成连接在电源线之间的电容器柱，使得MIM电容器中的电介质的故障导致可熔痕迹至少部分地断开，由此限制了在 电容柱。 此外，制造IC电容器组的方法包括提供连接到一对导电迹线的多个高k金属 - 绝缘体金属（MIM）电容器，并且在一对导电迹线的端部上定位可熔迹线以形成 连接在电源线之间的电容器柱，使得MIM电容器中的电介质的故障导致可熔痕迹至少部分地打开，从而限制电容器柱中的故障电流。

公开(公告)号：US08183696B2

公开(公告)日：2012-05-22

申请号：US12750946

申请日：2010-03-31

申请人： Thorsten Meyer ,  Rainer Leuschner ,  Gerald Ofner ,  Reinhard Hess ,  Recai Sezi

发明人： Thorsten Meyer ,  Rainer Leuschner ,  Gerald Ofner ,  Reinhard Hess ,  Recai Sezi

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/488 ,  H01L21/98

CPC分类号： H01L21/568 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/12105 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

摘要： A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is the pitch of the second contact pads in micrometers.

摘要翻译： 半导体封装包括半导体芯片，将半导体芯片嵌入的密封剂，在半导体封装的第一主面上的第一接触焊盘和与第一主面相对的半导体封装的第二主面上的第二接触焊盘。 第二接触焊盘的暴露的接触焊盘区域的直径d（以微米为单位）满足d≥（8/25）×+142μm，其中x是以微米为单位的第二接触焊盘的间距。

公开(公告)号：US20120122278A1

公开(公告)日：2012-05-17

申请号：US13007530

申请日：2011-01-14

申请人： Kwan Ho LEE ,  Yong Hui Joo ,  Tae Hyun KIM ,  Seog Moon CHOI

发明人： Kwan Ho LEE ,  Yong Hui Joo ,  Tae Hyun KIM ,  Seog Moon CHOI

IPC分类号： H01L21/98

CPC分类号： H01L24/83 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82801 ,  H01L2224/83192 ,  H01L2224/83238 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K3/3494 ,  H05K2201/09681 ,  H05K2203/1115 ,  H05K2203/1121 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/00012

摘要： Disclosed herein is a method of method of manufacturing a semiconductor package board, including: providing a substrate including a connection part formed on one side thereof, the connection part being provided thereon with a solder layer; disposing a conductive heat generator equipped with current wiring on the solder layer; applying current to the current wiring and thus heating the solder layer to attach a semiconductor chip to the connection part; and removing the current wiring from the conductive heat generator. The method is advantageous in that the semiconductor chip is attached to the substrate by applying current to the current wiring of the conductive heat generator to locally heat only the solder layer, thus reducing thermal stress and preventing the deformation of the substrate.

摘要翻译： 本发明公开了一种制造半导体封装板的方法，包括：提供包括形成在其一侧上的连接部分的基板，所述连接部分设置有焊料层; 在焊料层上配置配有电流布线的导电发热体; 向当前布线施加电流，从而加热焊料层以将半导体芯片附接到连接部分; 并从导电热发生器去除当前布线。 该方法的优点在于，通过向导电发热体的电流布线施加电流而将半导体芯片附接到基板，以仅局部加热焊料层，从而降低热应力并防止基板的变形。

公开(公告)号：US08153506B2

公开(公告)日：2012-04-10

申请号：US13100679

申请日：2011-05-04

申请人： Aya Anzai ,  Junya Maruyama

发明人： Aya Anzai ,  Junya Maruyama

IPC分类号： H01L21/98

CPC分类号： H01L27/1266 ,  G02F1/133305 ,  G02F2001/13613 ,  H01L27/1214 ,  H01L27/3244 ,  H01L51/0024 ,  H01L2251/5338 ,  Y10T428/31504

摘要： It is provided a contacting method when a plurality of films to be peeled are laminating. Reduction of total layout area, miniaturization of a module, weight reduction, thinning, narrowing a frame of a display device, or the like can be realized by sequentially laminating a plurality of films to be peeled which are once separately formed over a plastic film or the like. Moreover, reliable contact having high degree of freedom is realized by forming each layer having a connection face of a conductive material and by patterning with the use of a photomask having the same pattern.

摘要翻译： 当要剥离的多个薄膜层叠时，提供接触方法。 通过在塑料薄膜上依次层叠多个被剥离的薄膜，可以一次分开形成，可以实现总布局面积的减小，模块的小型化，减轻重量，变薄，缩小显示装置的框架等 类似。 此外，通过形成具有导电材料的连接面的各层，并通过使用具有相同图案的光掩模进行图案化，实现了高自由度的可靠接触。

公开(公告)号：US08133823B2

公开(公告)日：2012-03-13

申请号：US12247986

申请日：2008-10-08

申请人： Stefan Behler ,  Patrick Blessing

发明人： Stefan Behler ,  Patrick Blessing

IPC分类号： H01L21/98

CPC分类号： G05B19/4015 ,  G05B2219/37619 ,  G05B2219/39022 ,  G05B2219/39041 ,  G05B2219/45029 ,  G05B2219/45063 ,  G05B2219/49206 ,  G05B2219/50023 ,  H01L21/67144 ,  H01L21/67276 ,  H01L21/681 ,  H01L22/12

摘要： The invention relates to a method for picking up semiconductor chips from a wafer table and, optionally, their mounting on a substrate by means of a pick-and-place system. The position and orientation of the semiconductor chip to be mounted next are determined by means of a first camera and made available in the form of positional data relating to a first system of coordinates. The position and orientation of the substrate place on which the semiconductor chip will be mounted are determined by means of a second camera and made available in the form of positional data relating to a second system of coordinates. The conversion of coordinates of the first or second system of coordinates into coordinates of motion of the pick-and-place system occurs by means of two fixed mapping functions and two changeable correction vectors. The correction vectors are readjusted on the occurrence of a predetermined event.

摘要翻译： 本发明涉及一种用于从晶片台拾取半导体芯片的方法，并且可选地，通过拾取和放置系统将其安装在基板上。 接下来要安装的半导体芯片的位置和取向通过第一相机确定，并以与第一坐标系相关的位置数据的形式提供。 通过第二相机确定半导体芯片将要安装的基板位置的位置和取向，并以与第二坐标系相关的位置数据的形式提供。 通过两个固定映射函数和两个可更改的校正向量，将第一或第二坐标系坐标转换为拾取和放置系统的运动坐标。 在发生预定事件时重新调整校正矢量。

公开(公告)号：US20120056314A1

公开(公告)日：2012-03-08

申请号：US12874827

申请日：2010-09-02

申请人： Reza A. Pagaila ,  Dioscoro A. Merilo

发明人： Reza A. Pagaila ,  Dioscoro A. Merilo

IPC分类号： H01L23/50 ,  H01L21/98

CPC分类号： H01L23/562 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/495 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.

摘要翻译： 半导体器件具有带有第一和第二相对表面的基底基板。 在基底基板的第一表面上形成第一耐蚀刻导电层。 第二耐蚀刻导电层形成在基底衬底的第二表面上。 第一半导体管芯具有形成在第一管芯的有效表面上的接触焊盘上的凸起。 第一管芯安装在第一导电层的第一表面上。 密封剂沉积在第一管芯和基底衬底上。 去除基底衬底的一部分以在第一和第二导电层的相对部分之间形成电隔离的底部引线。 第二半导体管芯安装在密封剂上方，第一导电层的第二表面位于基底引线之间。 基部引线的高度大于第二管芯的厚度。

公开(公告)号：US20120027041A1

公开(公告)日：2012-02-02

申请号：US13256665

申请日：2010-03-08

申请人： Hiroyuki Yamazaki

发明人： Hiroyuki Yamazaki

IPC分类号： H01S5/026 ,  H01L21/98

CPC分类号： H01S5/4031 ,  G02B6/12004 ,  G02B6/4215 ,  G02B6/424 ,  G02B6/4245 ,  H01S5/02268 ,  H01S5/026 ,  H01S5/0265 ,  H01S5/12 ,  H01S5/4087 ,  H01S5/50

摘要： A wavelength variable laser includes: a substrate on which an optical coupler is formed as a planar optical waveguide; a DFB array part arranged on the substrate and having DFB laser elements respectively supply optical signals to the optical coupler; and an SOA part arranged on the substrate and having an SOA element configured to amplify an optical signal outputted from the optical coupler. The DFB array part and the SOA part are respectively formed in chips having a same lamination structure to each other. A wavelength variable laser and a modulator integrated wavelength variable laser with high yield ratio can be provided.

摘要翻译： 波长可变激光器包括：其上形成有光耦合器作为平面光波导的基板; 布置在基板上并具有DFB激光元件的DFB阵列部分分别向光耦合器提供光信号; 以及布置在所述基板上并且具有被配置为放大从所述光耦合器输出的光信号的SOA元件的SOA部件。 DFB阵列部分和SOA部分分别以彼此具有相同层压结构的芯片形成。 可以提供波长可变激光器和具有高屈服比的调制器集成波长可变激光器。

公开(公告)号：US20120012997A1

公开(公告)日：2012-01-19

申请号：US12835189

申请日：2010-07-13

申请人： Wen-Wei Shen ,  Yao-Chun Chuang ,  Chen-Shien Chen ,  Ming-Fa Chen

发明人： Wen-Wei Shen ,  Yao-Chun Chuang ,  Chen-Shien Chen ,  Ming-Fa Chen

IPC分类号： H01L23/50 ,  H01L21/60 ,  H01L21/98

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13669 ,  H01L2224/13684 ,  H01L2224/16148 ,  H01L2224/81193 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/01007 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00

摘要： A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

摘要翻译： 提供了可用于将一个衬底互连到另一衬底的凸块结构。 凹陷的导电柱形成在第一基板上，使得凹入的导电柱具有形成在其中的凹部。 凹部可以填充有焊料材料。 第二基板上的导电柱可以形成为具有宽度小于或等于凹部宽度的接触表面。 第一衬底可以附接到第二衬底，使得第二衬底上的导电柱位于第一衬底的凹部中或其中。 基板可以各自为集成电路管芯，插入件，印刷电路板，高密度互连等。

公开(公告)号：US20110309484A1

公开(公告)日：2011-12-22

申请号：US13069390

申请日：2011-03-23

申请人： WANG-LAI YANG

发明人： WANG-LAI YANG

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/98

CPC分类号： H01R43/00 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A semiconductor package includes a lead frame, a first chip, a second chip, a plurality of bonding wires and a mold compound. The lead frame includes a pad portion at a center of the frame and a plurality of lead portions. The pad portion and the plurality of lead portions collectively define a receiving portion. The first chip is securely received in the receiving portion. The second chip is mechanically attached to the first chip. The plurality of bonding wires electrically connect the second chip to the plurality of lead portions. The mold compound encapsulates the lead frame, the first chip, the second chip and the plurality of bonding wires to form the semiconductor package.

摘要翻译： 半导体封装包括引线框架，第一芯片，第二芯片，多个接合线和模具化合物。 引线框架包括在框架的中心处的焊盘部分和多个引线部分。 焊盘部分和多个引线部分共同限定接收部分。 第一芯片牢固地接收在接收部分中。 第二芯片机械连接到第一芯片。 多个接合线将第二芯片电连接到多个引线部分。 模具化合物封装引线框架，第一芯片，第二芯片和多个接合线以形成半导体封装。

公开(公告)号：US20110291231A1

公开(公告)日：2011-12-01

申请号：US12788297

申请日：2010-05-27

申请人： Li Jiang ,  Ryan J. Hurley ,  Sudhama C. Shastri ,  Yenting Wen ,  Wang-Chang Albert Gu ,  Phillip Holland ,  Der Min Liou ,  Rong Liu ,  Wenjiang Zeng

发明人： Li Jiang ,  Ryan J. Hurley ,  Sudhama C. Shastri ,  Yenting Wen ,  Wang-Chang Albert Gu ,  Phillip Holland ,  Der Min Liou ,  Rong Liu ,  Wenjiang Zeng

IPC分类号： H01L23/538 ,  H01L21/98

CPC分类号： H01L23/5227 ,  H01L23/66 ,  H01L28/10 ,  H01L2223/6638 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.

摘要翻译： 一种半导体元件及其制造方法，该半导体元件包括单片集成的共模扼流圈。 根据实施例，瞬态电压抑制装置可以耦合到单片集成的共模扼流圈。