公开(公告)号：US20190027537A1

公开(公告)日：2019-01-24

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. WIEGAND ,  Oleg GOLONZKA ,  MD Tofizur RAHMAN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Tahir GHANI ,  Satyarth SURI

IPC: H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  H01L23/528 ,  H01L43/02 ,  H01L23/532 ,  H01L43/12 ,  H01L21/768 ,  H01F41/32

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/32 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/226 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of dielectric layer above a substrates, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20160233298A1

公开(公告)日：2016-08-11

申请号：US15024750

申请日：2013-12-19

Applicant: INTEL CORPORATION

Inventor： Milton C. WEBB ,  Mark BOHR ,  Tahir GHANI ,  Szuya S. LIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

Abstract translation: 描述了自对准栅极边缘和局部互连结构以及制造自对准栅极边缘和局部互连结构的方法。 在一个示例中，半导体结构包括设置在基板上方并且具有沿第一方向的长度的半导体鳍片。 栅极结构设置在半导体鳍上方，栅极结构具有与第一方向正交的第二端相对于第二端的第一端。 一对栅极边缘隔离结构以半导体鳍为中心。 一对栅极边缘隔离结构中的第一个直接邻近栅极结构的第一端设置，并且该对栅极边缘隔离结构中的第二个直接邻近栅极结构的第二端设置。

公开(公告)号：US20160155815A1

公开(公告)日：2016-06-02

申请号：US14998092

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/16 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20150200301A1

公开(公告)日：2015-07-16

申请号：US14667544

申请日：2015-03-24

Applicant: Intel Corporation

Inventor： Jacob Jensen ,  Tahir GHANI ,  Mark Y. LIU ,  Harold KENNEL ,  Robert JAMES

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

Abstract translation: 一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。 升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。 超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。 翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。 进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。

公开(公告)号：US20250151338A1

公开(公告)日：2025-05-08

申请号：US19016771

申请日：2025-01-10

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC: H10D30/67 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

公开(公告)号：US20250113607A1

公开(公告)日：2025-04-03

申请号：US18978616

申请日：2024-12-12

Applicant: Intel Corporation

Inventor： Martin D. GILES ,  Tahir GHANI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

公开(公告)号：US20250022939A1

公开(公告)日：2025-01-16

申请号：US18900094

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Tahir GHANI ,  Atul MADHAVAN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

公开(公告)号：US20240347595A1

公开(公告)日：2024-10-17

申请号：US18410681

申请日：2024-01-11

Applicant: Intel Corporation

Inventor： William HSU ,  Biswajeet GUHA ,  Leonard GULER ,  Souvik CHAKRABARTY ,  Jun Sung KANG ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  B82Y10/00

CPC classification number: H01L29/0673 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  B82Y10/00

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

公开(公告)号：US20240274718A1

公开(公告)日：2024-08-15

申请号：US18643632

申请日：2024-04-23

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/165 ,  H01L29/66818 ,  H01L29/7851

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20240243203A1

公开(公告)日：2024-07-18

申请号：US18622659

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/02603 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/42392 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.