公开(公告)号：US06485814B1

公开(公告)日：2002-11-26

申请号：US09513162

申请日：2000-02-25

Applicant: Kiyokazu Moriizumi ,  Mikio Nishihara

Inventor： Kiyokazu Moriizumi ,  Mikio Nishihara

IPC: B32B300

CPC classification number: H01L23/49811 ,  H01L2224/1147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0305 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10318 ,  H05K2203/1581 ,  Y10T428/24926 ,  H01L2224/0401

Abstract: To provide electrical conduction between front and back surfaces of a thin film multi-layered circuit board, such as an MCM, at low cost without using a simultaneous firing process for ceramic. The thin film multi-layered circuit board has at least one thin film circuit layer on a first surface of a substrate, wherein a conductor layer is disposed in the lowermost layer of the thin film circuit layer in contact with the first surface of the substrate, and is characterized in that holes for providing the electrical conduction between front and back surfaces of the substrate are formed through the substrate from the first surface to a second surface thereof so that the conductor layer is exposed in the hole, wherein the diameter of the hole is gradually enlarged from the first surface to the second surface.

Abstract translation: 以低成本提供薄膜多层电路板（例如MCM）的前后表面之间的导电，而不需要使用陶瓷的同时烧制工艺。 薄膜多层电路板在基板的第一表面上具有至少一个薄膜电路层，其中导体层设置在与基板的第一表面接触的薄膜电路层的最下层中， 并且其特征在于，通过基板从基板的第一表面到第二表面形成用于提供基板的前表面和后表面之间的导电的孔，使得导体层暴露在孔中，其中孔的直径 从第一表面逐渐增大到第二表面。

公开(公告)号：US06466113B1

公开(公告)日：2002-10-15

申请号：US09489505

申请日：2000-01-21

Applicant: E. James Crescenzi, Jr. ,  Anwar A. Mohammed

Inventor： E. James Crescenzi, Jr. ,  Anwar A. Mohammed

IPC: H05K118

CPC classification number: H05K3/44 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0047 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09554 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/171 ,  H05K2203/175 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit architecture includes a relatively thick, stiffening base of thermally and electrically conductive material, and a laminate of conductive layers including a printed circuit structure, interleaved with dielectric layers, disposed atop the base. The patterned conductive layers contain an integrated circuit structure that is configured to provide RF signaling, microstrip shielding, and digital and analog control signal leads, and DC power. Low inductance electrical connectivity among the conductive layers and also between conductive layers and the base is provided by a plurality of conductive bores. Selected bores are counter-drilled at the RF signaling layer and filled with insulating plugs, which prevent shorting of the RF signal trace layer to ground, during solder reflow connection of leads of circuit components to the RF signaling layer.

Abstract translation: 印刷电路架构包括相对厚的加热和导电材料的加强基底，以及布置在基底顶部的包括与电介质层交织的印刷电路结构的导电层的层压体。 图案化导电层包含被配置为提供RF信号，微带屏蔽以及数字和模拟控制信号引线以及DC电力的集成电路结构。 导电层之间以及导电层和基底之间的低电感电连接由多个导电孔提供。 选择的孔在RF信号层反相钻孔，并填充有绝缘插头，以防止将RF信号迹线层短路到地，将电路部件的引线与RF信号层焊接回流连接。

公开(公告)号：US20020130739A1

公开(公告)日：2002-09-19

申请号：US10046323

申请日：2002-01-14

Inventor： Martin A. Cotton

IPC: H01P003/08

CPC classification number: H05K1/0218 ,  H01L23/552 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H05K1/0221 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/0041 ,  H05K3/4652 ,  H05K2201/09036 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2201/09981 ,  H01L2224/0401

Abstract: Construction of printed circuit boards (PCBs) containing electromagnetic shielding and conductive tubes forming signal lines and/or waveguides. The method of construction calls for forming of grooves through layers of the PCB and coating the interior surfaces of these grooves with conductive material. These conductor-coated groove walls serve as conductive surfaces between embedded conductive surfaces on different layers. The conductive surfaces thus joined form a continuous electrically conductive surface that can be configured to act as an electromagnetic shield. Such conductive surfaces may be configured with internal conductors to act as a signal line, or without internal conductors to act as a waveguide.

Abstract translation: 构造包含电磁屏蔽和形成信号线和/或波导的导电管的印刷电路板（PCB）。 施工方法要求通过PCB的层形成凹槽，并用导电材料涂覆这些凹槽的内表面。 这些导体涂覆的槽壁用作不同层上的嵌入的导电表面之间的导电表面。 这样连接的导电表面形成连续的导电表面，该表面可配置为充当电磁屏蔽。 这样的导电表面可以配置有内部导体以用作信号线，或者不具有用作波导的内部导体。

公开(公告)号：US06452116B2

公开(公告)日：2002-09-17

申请号：US09796389

申请日：2001-02-28

Applicant: Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffrey S. Perkins ,  John J. Pessarchick

Inventor： Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffrey S. Perkins ,  John J. Pessarchick

IPC: H01R909

CPC classification number: H05K1/112 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144

Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of placing one or more blind vias in a first substrate positioned on top of a first conductor; placing one or more blind vias in a second substrate positioned under a second conductor; attaching one or more signal lines to one or more of the one or more blind vias; and assembling ball grid array components such that the first conductor is electrically connected to the second conductor. Also claimed is an electronic circuit package incorporating the blind vias for electrical connection between layers in accordance with the present invention.

Abstract translation: 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：将一个或多个盲孔放置在位于第一导体顶部的第一衬底中; 将一个或多个盲孔放置在位于第二导体下方的第二衬底中; 将一个或多个信号线附接到所述一个或多个盲孔中的一个或多个; 以及组装球栅阵列部件，使得第一导体电连接到第二导体。 还要求保护的是一种电子电路封装，其包括用于根据本发明的层之间的电连接的盲孔。

公开(公告)号：US20020104669A1

公开(公告)日：2002-08-08

申请号：US09775460

申请日：2001-02-05

Inventor： Jeffrey A. Underwood ,  John K. Arledge ,  Thomas J. Swirbel ,  Joaquin Barreto

IPC: H05K009/00

CPC classification number: H05K1/0218 ,  H01L2223/6622 ,  H05K1/0221 ,  H05K1/0222 ,  H05K1/113 ,  H05K3/4644 ,  H05K9/0039 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09809 ,  H05K2201/09972 ,  H05K2201/09981 ,  H05K2201/10553 ,  H05K2201/10969 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Methods and apparatus for forming a metal shield on a printed circuit board (10) include a layer of dielectric material (23) one or more printed circuits (21) on the layer of dielectric material (23), a layer of metal (27) on the layer of dielectric material (23), a metal-clad trench or opening surrounding the printed circuit (44) and electrically connected to the layer of metal (27), a solder pad (24) on the layer of dielectric material (23), a microvia (25) through the solder pad (24) and the layer of dielectric material (23), and electrical components (11) soldered to the solder pads (24) and to the printed circuit (21).

Abstract translation: 在印刷电路板（10）上形成金属屏蔽的方法和装置包括介电材料层（23），介电材料层（23）上的一个或多个印刷电路（21），金属层（27） 在电介质材料层（23）上，围绕印刷电路（44）并电连接到金属层（27）的金属包覆沟槽或开口，介电材料层（23）上的焊盘（24） ），通过焊盘（24）和电介质材料层（23）的微孔（25）以及焊接到焊盘（24）和印刷电路（21）的电气部件（11）。

公开(公告)号：US20020092676A1

公开(公告)日：2002-07-18

申请号：US09761124

申请日：2001-01-16

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

IPC: H05K001/03 ,  H05K001/09 ,  H05K001/11 ,  H05K003/10

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

Abstract translation: 提供电子封装和制造电子封装的方法。 电介质材料层位于包括多个导电触点的衬底的第一表面上。 至少一个通孔形成在电介质材料层中，与多个导电触点中的至少一个对准。 导电材料位于基本上填充通孔的至少一个通孔中。 至少一个导电构件定位在通孔中的导电材料上并与导电材料电接触。 该电子封装提高了组件的现场使用寿命，该组件包括附接到衬底的第二表面的半导体芯片和附着到导电构件的印刷线路板。

公开(公告)号：US06408511B1

公开(公告)日：2002-06-25

申请号：US09643387

申请日：2000-08-21

Applicant: Shaul Branchevsky

Inventor： Shaul Branchevsky

IPC: H01R900

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/245 ,  H05K3/321 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for providing an enhanced ball grid array attachment in low-temperature co-fired ceramic (LTCC) substrate is provided. A termination cup is formed in a substrate. The termination cup has a bottom formed by a termination pad over a via in a first tape layer and side walls formed by termination sides formed over side walls of a via in a second tape layer. A diffusion layer is formed over the termination cup. The diffusion layer helps to reduce the oxidation of the termination cup and to provide greater mechanical attachment strength. An electrically conductive adhesive may be used to connect a solder ball to the diffusion layer. Reflow then is used to complete the solder ball connection process.

Abstract translation: 提供了一种用于在低温共烧陶瓷（LTCC）衬底中提供增强的球栅阵列附件的方法。 终端杯形成在基板中。 终端杯具有由第一带层中的通孔上的终端焊盘形成的底部，并且由在第二带层中的通孔的侧壁上形成的端接端形成的侧壁。 在终端杯上形成扩散层。 扩散层有助于减少端接杯的氧化并提供更大的机械附着强度。 可以使用导电粘合剂将焊球连接到扩散层。 回流则用于完成焊球连接过程。

公开(公告)号：US06404081B1

公开(公告)日：2002-06-11

申请号：US09637291

申请日：2000-08-11

Applicant: Donald T. Staffiere

Inventor： Donald T. Staffiere

IPC: H01H3500

CPC classification number: H02J9/06 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/16 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/10037 ,  Y10T307/625 ,  Y10T307/858

Abstract: A backup energy unit for an electrical device having a power source, an operational load, and containing a layered electrical device having a top exterior surface and a bottom exterior surface, such as an integrated chip or layered circuit board. The energy unit is made up of at least one energy storage device. This energy storage device is made up of a dielectric material and a first and a second electrical storage conducting layer. The dielectric material lies between the first and second electrical storage conducting layers. Further, the dielectric material exists between the top exterior surface and bottom exterior surface of the layered electrical device. The energy unit is further made up of a voltage detector to detect a potential level of the power source. When the voltage detector detects a power source disruption, that is when the potential level of the power source is below a first voltage state, it controls a switcher. This switcher disconnects the power source from the operational load and connects the energy storage device to the operational load when the voltage detector detects a power source disruption. Thus, when the power source is disrupted, the energy storage device provides electrical power to the operational load.

Abstract translation: 一种用于具有电源，操作负载并且包含具有顶部外表面和底部外表面的分层电气设备（诸如集成芯片或分层电路板）的电气设备的备用能量单元。 能量单元由至少一个储能装置组成。 该储能装置由电介质材料和第一和第二蓄电层构成。 电介质材料位于第一和第二电存储导电层之间。 此外，电介质材料存在于分层电气装置的顶部外表面和底部外表面之间。 能量单元进一步由电压检测器组成，以检测电源的电位。 当电压检测器检测到电源中断时，即当电源的电位低于第一电压状态时，它控制切换器。 当电压检测器检测到电源中断时，该切换器将电源与操作负载断开连接，并将能量存储设备连接到操作负载。 因此，当电源中断时，能量存储装置向操作负载提供电力。

公开(公告)号：US20020067452A1

公开(公告)日：2002-06-06

申请号：US10056036

申请日：2002-01-28

Applicant: NEC CORPORATION

Inventor： Michiaki Sakamoto ,  Choei Sugitani

IPC: G02F001/1343

CPC classification number: G02F1/13458 ,  G02F1/13452 ,  H05K1/111 ,  H05K1/112 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/0969

Abstract: In an active matrix liquid-crystal display device, dummy contact holes are provided between neighboring terminals, so as to prevent a poor connection between the lower metal layer of a terminal and a TAB caused by conductive particles of an ACF remaining on an organic film, and contact holes that make connections between an upper layer transparent electrode of a terminal and a lower metal layer are formed by a plurality of fine via holes, so that sufficient conductive particles of the ACF remain on the upper transparent electrode and a good connection is made to TAB connection lines.

Abstract translation: 在有源矩阵液晶显示装置中，在相邻端子之间设置虚拟接触孔，以防止端子的下部金属层与残留在有机膜上的ACF的导电粒子引起的TAB之间的连接不良， 并且通过多个精细通孔形成通过多个细小通孔形成端子的上层透明电极与下部金属层之间的连接的接触孔，使得足够的ACF导电颗粒残留在上部透明电极上并形成良好的连接 到TAB连接线。

公开(公告)号：US06400028B1

公开(公告)日：2002-06-04

申请号：US09119467

申请日：1998-07-20

Applicant: Edward Allyn Burton

Inventor： Edward Allyn Burton

IPC: H01L2940

CPC classification number: H05K1/115 ,  H05K1/0231 ,  H05K1/114 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09854

Abstract: An improvement is presented for connecting conductive components of a built-up circuit board. Rather than using vias or micro vias to connect a conductive layer to a conductive component separated by an insulating layer, an elongated via is used. In one embodiment, the elongated via has a length that is sufficient to directly coupled a first layer to the edge of a via in a lower layer. Thus, it can be said that the elongated via “self-aligns” with the via in the lower layer. In doing so, electrical connections from one side of a circuit board to a component coupled to the other side of the circuit board are more direct leading to a reduction in parasitic induction.

Abstract translation: 提出了用于连接积层电路板的导电部件的改进。 不是使用通孔或微通孔将导电层连接到由绝缘层分离的导电部件，而是使用细长的通孔。 在一个实施例中，细长通孔具有足以将第一层直接耦合到下层中的通孔的边缘的长度。 因此，可以说细长通孔与下层中的通孔“自对准”。 在这样做时，从电路板的一侧到耦合到电路板的另一侧的部件的电连接更直接地导致寄生感应的减小。