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公开(公告)号：US08522430B2
公开(公告)日：2013-09-03
申请号：US13549440
申请日：2012-07-14
IPC分类号： H05K3/40 , H01L21/768 , H01L23/48
CPC分类号： H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
摘要： A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
摘要翻译： 在衬底/芯片组件中制造衬底通孔结构的方法包括以下步骤：在衬底/芯片组件中布置用于电互连的中心通孔叠层; 以及通过堆叠提供围绕中心的多个堆叠的通孔。 多个堆叠的通孔通过堆叠环绕中心，导致结构上没有隔离的通孔堆叠。 多个堆叠的通孔具有功能和非功能通孔。
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公开(公告)号：US20120309187A1
公开(公告)日：2012-12-06
申请号：US13194902
申请日：2011-07-29
IPC分类号： H01L21/60
CPC分类号： H01L24/11 , H01L21/4853 , H01L23/145 , H01L23/49816 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/1184 , H01L2224/11849 , H01L2224/131 , H01L2224/16225 , H01L2224/81193 , H01L2224/81815 , H01L2924/10253 , H01L2924/3511 , H01L2924/014 , H01L2924/00
摘要： Thermal deformation of a substrate and the substrate's warp at room temperature are used to determine the expected profile of the substrate at reflow. A contact surface profile of a coining pressure plate is selected based on the expected substrate profile. A solder surface is shaped on the substrate or a die to be joined to the substrate by the coining pressure plate, thereby facilitating the chip-joining process.
摘要翻译： 使用基板的热变形和基板在室温下的翘曲来确定基板在回流时的预期分布。 基于预期的基底轮廓来选择压印压板的接触表面轮廓。 焊料表面通过压印压力板在基板上或模具上成形，从而便于芯片接合工艺。
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公开(公告)号：US20120279061A1
公开(公告)日：2012-11-08
申请号：US13549440
申请日：2012-07-14
IPC分类号： H05K3/40
CPC分类号： H01L23/49827 , H01L23/498 , H01L23/49838 , H01L2224/05001 , H01L2224/05008 , H01L2224/05572 , H01L2224/16 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H05K1/0222 , H05K1/115 , H05K3/4602 , H05K2201/096 , H05K2201/09609 , Y10T29/49155 , Y10T29/49165 , Y10T29/4919 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599 , H01L2224/05099
摘要： A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.
摘要翻译： 在衬底/芯片组件中制造衬底通孔结构的方法包括以下步骤：在衬底/芯片组件中布置用于电互连的中心通孔叠层; 以及通过堆叠提供围绕中心的多个堆叠的通孔。 多个堆叠的通孔通过堆叠环绕中心，导致结构上没有隔离的通孔堆叠。 多个堆叠的通孔具有功能和非功能通孔。
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24.发明授权Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法公开(公告)号：US08258410B2
公开(公告)日：2012-09-04
申请号：US12020534
申请日：2008-01-26
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing.
摘要翻译： 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 平板通孔着陆包括顺应中心区域; 以及用于连接板状通孔底板的柔性中心区域的弹簧状刚度减小连接器。
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公开(公告)号：US08085550B2
公开(公告)日：2011-12-27
申请号：US12410095
申请日：2009-03-24
IPC分类号： H05K7/10
CPC分类号： H05K1/111 , H01R43/0256 , H05K3/3421 , H05K2201/0373 , H05K2201/09736 , H05K2201/2036 , Y02P70/611 , Y02P70/613 , Y10T29/49218
摘要： A method and a surface mount technology (SMT) pad structure are provided for implementing enhanced solder joint robustness. The SMT pad structure includes a base SMT pad. The base SMT pad receives a connector for soldering to the SMT pad structure. A standoff structure having a selected geometry is defined on the base SMT pad to increase thickness of the solder joint for the connector.
摘要翻译： 提供了一种方法和表面贴装技术（SMT）焊盘结构，用于实现增强的焊点鲁棒性。 SMT焊盘结构包括基板SMT焊盘。 基座SMT焊盘接收用于焊接到SMT焊盘结构的连接器。 在基座SMT焊盘上限定具有选定几何形状的间隔结构，以增加用于连接器的焊点的厚度。
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26.发明授权公开(公告)号：US08054630B2
公开(公告)日：2011-11-08
申请号：US12030260
申请日：2008-02-13
申请人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人： David Questad , Vijayeshwar D. Khanna , Jennifer V. Muney , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
IPC分类号： H05K7/20
CPC分类号： H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要： A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.
摘要翻译： 将电子部件安装在基板上的方法包括在基板的表面中形成至少一个沟槽。 形成在衬底中的沟槽降低了衬底的刚度，这提供了较小的剪切阻力。 因此，沟槽减少了将电子部件安装到基板上的接头上的应变量，这增加了接头的寿命。
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27.发明授权Elliptic C4 with optimal orientation for enhanced reliability in electronic packages 有权椭圆C4具有最佳的方向，增强电子封装的可靠性公开(公告)号：US08047421B2
公开(公告)日：2011-11-01
申请号：US12869340
申请日：2010-08-26
IPC分类号： B23K31/02
CPC分类号： B23K1/0016 , B23K2101/40 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L2224/0401 , H01L2224/06051 , H01L2224/16225 , H01L2224/16227 , H01L2224/17051 , H01L2924/01004 , H01L2924/10253 , H05K1/111 , H05K3/3436 , H05K2201/09381 , H05K2201/094 , H05K2201/10734 , Y02P70/611 , Y02P70/613 , H01L2924/00
摘要： An arrangement for the equipping of electronic packages with elliptical C4 connects possessing optimal orientation for enhanced reliability. Furthermore, disclosed is a method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages. Employed are essentially elliptical solder pads or elliptical C4 pad configurations at various preferably corner locations on a semiconductor chip.
摘要翻译： 用于配备具有椭圆形C4连接的电子封装的布置具有最佳取向以增强可靠性。 此外，公开了一种提供椭圆形C4连接的方法，其具有与其安装在电子封装中相关联的实现的用于增强可靠性的最佳取向。 在半导体芯片上的各种优选拐角位置处，基本上是椭圆形的焊盘或椭圆形的C 4焊盘配置。
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28.发明授权System and method for sensor replication for ensemble averaging in micro-electromechanical system (MEMS) 有权用于微机电系统（MEMS）中的系统平均的传感器复制的系统和方法公开(公告)号：US07904185B2
公开(公告)日：2011-03-08
申请号：US12165134
申请日：2008-06-30
申请人： Sri M. Sri-Jayantha , Arun Sharma , Hien Dang , Evangelos S. Eleftheriou , Mark A. Lantz , Charalampos Pozidis
发明人： Sri M. Sri-Jayantha , Arun Sharma , Hien Dang , Evangelos S. Eleftheriou , Mark A. Lantz , Charalampos Pozidis
IPC分类号： G05B13/02
CPC分类号： G01D3/08 , G01K2215/00
摘要： A MEMs-based system (and method), includes a sensor array including at least two sensors providing a basis for ensemble averaging.
摘要翻译： 基于MEM的系统（和方法）包括传感器阵列，其包括至少两个传感器，为集合平均提供基础。
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29.发明申请公开(公告)号：US20100276784A1
公开(公告)日：2010-11-04
申请号：US12783787
申请日：2010-05-20
申请人： David Questad , Vijayeshwar D. Kharma , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
发明人： David Questad , Vijayeshwar D. Kharma , Jennifer V. Muncy , Arun Sharma , Sri M. Sri-Jayantha , Lorenzo Valdevit
CPC分类号： H01L28/40 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0231 , H05K1/0271 , H05K1/111 , H05K3/3436 , H05K3/3442 , H05K2201/09036 , H05K2201/10015 , H05K2201/10727 , Y02P70/613 , Y10T29/4913 , Y10T428/24479 , H01L2224/0401 , H01L2924/00
摘要： An electronic module including a substrate having at least one structure that reduces stress flow through the substrate, wherein the structure comprises at least one trench in a surface of the substrate.
摘要翻译： 一种电子模块，包括具有至少一个结构的衬底，所述结构减少了通过衬底的应力流动，其中所述结构包括在所述衬底的表面中的至少一个沟槽。
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30.发明申请Method to Extract and Apply Circuit Features in Organic Substrate for Automation of Warp Modeling 失效在有机基板中提取和应用电路特征的方法，用于自动化变形建模公开(公告)号：US20090313588A1
公开(公告)日：2009-12-17
申请号：US12260957
申请日：2008-10-29
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , H05K1/0271 , H05K2201/09136
摘要： A method of characterizing an organic substrate including a plurality of circuit layers is provided includes the steps of: receiving an image of the organic substrate, the image including a geometric description of the circuit layers of the substrate; segmenting the substrate into multiple processing regions based, at least in part, on geometric coordinates of circuit structures defined in the image of the substrate; generating a circuit layer image corresponding to a selected one of the processing regions of the substrate; identifying one or more geometric features in the circuit layer image; estimating at least one thermomechanical property of the circuit layer image as a function of the identified geometric features; repeating the steps of receiving an image, generating a circuit layer image, identifying one or more geometric features in the circuit layer image, and estimating at least one thermomechanical property of the circuit layer image until all circuit layers in the substrate have been processed; and generating a 3-D representation of the selected one of the processing regions of the substrate including the plurality of circuit layer images as a function of the at least one thermomechanical property of each of the plurality of circuit layer images.
摘要翻译： 提供了表征包括多个电路层的有机衬底的方法包括以下步骤：接收有机衬底的图像，该图像包括衬底的电路层的几何描述; 至少部分地基于在衬底的图像中限定的电路结构的几何坐标将衬底分割成多个处理区域; 生成与所述基板的所述选择的一个所述处理区域对应的电路层图像; 识别电路层图像中的一个或多个几何特征; 估计电路层图像的至少一个热机械性质作为所识别的几何特征的函数; 重复接收图像的步骤，生成电路层图像，识别电路层图像中的一个或多个几何特征，以及估计电路层图像的至少一个热机械特性，直到已经处理了基板中的所有电路层; 以及根据所述多个电路层图像中的每一个的所述至少一个热机械特性，生成包括所述多个电路层图像的所述基板的所选择的一个处理区域的3-D表示。
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