公开(公告)号：US09691701B2

公开(公告)日：2017-06-27

申请号：US15018951

申请日：2016-02-09

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu

IPC: H01L29/49 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/16 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2224/81

Abstract: In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit may include a plurality of wiring layers. At least one metal-insulator-metal (MIM) capacitor may be formed within the plurality of wiring layers. The integrated circuit may include a circuit. The circuit may include at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die. The circuit may be coupled substantially below at least a portion of the MIM capacitor in the plurality of layers. The circuit may be electrically coupled to the capacitor through the plurality of wiring layers. The integrated circuit may include a plurality of electrical connectors, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit.

公开(公告)号：US20170089783A1

公开(公告)日：2017-03-30

申请号：US15373360

申请日：2016-12-08

Applicant: Apple Inc.

Inventor： Caleb C. Han ,  Tongbi Jiang ,  Jun Zhai

IPC: G01L7/08 ,  B81C1/00 ,  B81B7/00

CPC classification number: G01L7/08 ,  B81B7/0048 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C2203/0792 ,  G01L9/0045 ,  G01L9/0048 ,  G01L19/0618 ,  G01L19/146 ,  G01L19/148 ,  H01L41/094 ,  H01L41/1136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48095 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/16195

Abstract: Sensor packages and manners of formation are described. In an embodiment, a sensor package includes a supporting die characterized by a recess area and a support anchor protruding above the recess area. A sensor die is bonded to the support anchor such that an air gap exists between the sensor die and the recess area. The sensor die includes a sensor positioned directly above the air gap.

公开(公告)号：US09595526B2

公开(公告)日：2017-03-14

申请号：US14077512

申请日：2013-11-12

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Emerson S. Fang ,  Jun Zhai ,  Shawn Searles

IPC: H01L21/02 ,  H01L27/10 ,  H01L23/48 ,  H01L23/13 ,  H01L23/64 ,  H01L25/16 ,  H01L25/18 ,  H01G4/228 ,  H01L49/02 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L27/101 ,  H01G4/228 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12042 ,  H01L2924/1205 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

Abstract translation: 描述了包括电力消耗装置（例如SOC装置）的半导体器件封装。 电力消耗装置可以包括一个或多个电流消耗元件。 无源设备可以耦合到功率消耗设备。 无源器件可以包括形成在半导体衬底上的多个无源元件。 无源元件可以布置在半导体衬底上的结构阵列中。 功率消耗装置和无源装置可以使用一个或多个终端来耦合。 无源器件和功耗器件耦合可以被配置成使得功率消耗器件功能地确定无源器件元件将被使用的方式。

公开(公告)号：US09583472B2

公开(公告)日：2017-02-28

申请号：US14637109

申请日：2015-03-03

Applicant: Apple Inc.

Inventor： Chih-Ming Chung ,  Jun Zhai ,  Yizhang Yang

IPC: H01L25/18 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/34 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/14 ,  H01L24/19 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL），第一和第二RDL之间的堆叠管芯，以及在RDL之间延伸的导电柱。 模塑料可以将堆叠的管芯和导电柱塞在第一和第二RDL之间。

公开(公告)号：US20170018546A1

公开(公告)日：2017-01-19

申请号：US15057588

申请日：2016-03-01

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/77

CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

Abstract translation: 在一些实施例中，系统可以包括集成电路。 集成电路可以包括包括第一表面，基本上与第一表面相对的第二表面的衬底和耦合到第一表面的第一组电导体。 第一组电导体可以用于将集成电路电连接到电路板。 集成电路可以包括使用第二组电导体耦合到衬底的第二表面的半导体管芯。 集成电路可以包括被定义为与集成电路集成的无源器件。 无源器件可以位于第二表面和第一组电导体中的至少一个之间。 芯片可以电连接到无源器件的第二侧。 无源器件的第一侧可用于电连接到第二器件。

公开(公告)号：US20160315071A1

公开(公告)日：2016-10-27

申请号：US14804261

申请日：2015-07-20

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/19

Abstract: Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer.

Abstract translation: 描述了包装结构中的垂直堆叠系统。 在一个实施例中，包装包括第一级成型和扇出结构，第三级成型和扇出结构，以及第一级和第三级之间的第二级成型和扇出结构。 第二级成型和扇出结构包括背对背模具，每个模具的前表面结合到再分配层。

公开(公告)号：US20160260684A1

公开(公告)日：2016-09-08

申请号：US14638925

申请日：2015-03-04

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Kwan-Yu Lai ,  Mengzhi Pang ,  Chonghua Zhong ,  Se Young Yang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。

公开(公告)号：US20160137488A1

公开(公告)日：2016-05-19

申请号：US14543468

申请日：2014-11-17

Applicant: Apple Inc.

Inventor： Tongbi Jiang ,  Jun Zhai

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0048 ,  B81B2207/012 ,  B81C1/00325 ,  B81C2203/0154

Abstract: MEMS packages and modules are described. In an embodiment, a module includes a package mounted within an opening in a module board. The package includes a flexible wiring board mounted to a back surface of the module board and spanning across the opening in the module board. A die is mounted on the flexible wiring board and is encapsulated within an overmold. An air gap exists laterally between the overmold and side surface of the opening in the module board.

Abstract translation: 描述了MEMS封装和模块。 在一个实施例中，模块包括安装在模块板中的开口内的封装。 该封装包括安装到模块板的背面并横跨模块板的开口的柔性布线板。 模具安装在柔性布线板上并被封装在包覆模制中。 在模块板的开口的包覆模制和侧表面之间横向存在气隙。

公开(公告)号：US20150230342A1

公开(公告)日：2015-08-13

申请号：US14244299

申请日：2014-04-03

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H05K3/00 ,  H05K1/11 ,  H05K1/03

CPC classification number: H05K1/115 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/029 ,  H05K2201/09581 ,  Y10T29/49124 ,  H01L2924/00

Abstract: In some embodiments, a carrier substrate for an integrated circuit may include a core, a first plurality of openings, and a first insulating material. The core may include a first surface and a second surface substantially opposing the first surface. The first plurality of openings may extend from the first surface to the second surface of the core. In some embodiments, the first insulating material may be applied to a surface of the first plurality of openings. In some embodiments, the first plurality of openings may include a first conductor extending through each of the first plurality of openings from the first surface to the second surface. In some embodiments, at least a first subset of the first plurality of openings may include a first charge and at least a second subset of the first plurality of openings may include a second charge. The first charge and the second charge may be different.

Abstract translation: 在一些实施例中，用于集成电路的载体衬底可以包括芯，第一多个开口和第一绝缘材料。 芯可以包括基本上与第一表面相对的第一表面和第二表面。 第一多个开口可以从芯的第一表面延伸到第二表面。 在一些实施例中，第一绝缘材料可以施加到第一多个开口的表面。 在一些实施例中，第一多个开口可以包括延伸穿过第一多个开口中的每一个从第一表面到第二表面的第一导体。 在一些实施例中，第一多个开口的至少第一子集可以包括第一电荷，并且第一多个开口的至少第二子集可以包括第二电荷。 第一次充电和第二次充电可能不同。

公开(公告)号：US20250112154A1

公开(公告)日：2025-04-03

申请号：US18643907

申请日：2024-04-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Antonietta Oliva ,  Sambasivan Narayan ,  Jun Zhai ,  Vidhya Ramachandran ,  Kamal Sikka

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/427 ,  H01L23/473 ,  H01L23/48 ,  H01L23/522

Abstract: Chip structures and electronic modules including a power delivery network (PDN) routing structure and signal routing structure to balance power, signaling, and thermal requirements are described. In an embodiment, the chip includes a device layer, a PDN routing structure on top of the device layer, and a signal routing structure underneath the device layer.