公开(公告)号：US09093332B2

公开(公告)日：2015-07-28

申请号：US13023011

申请日：2011-02-08

申请人： Tin-Hao Kuo ,  Yu-Feng Chen ,  Chen-Shien Chen ,  Chen-Hua Yu ,  Sheng-Yu Wu ,  Chita Chuang

发明人： Tin-Hao Kuo ,  Yu-Feng Chen ,  Chen-Shien Chen ,  Chen-Hua Yu ,  Sheng-Yu Wu ,  Chita Chuang

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14141 ,  H01L2224/81192 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2924/00

摘要： An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump.

摘要翻译： 提供了用于半导体器件的细长凸块结构。 最上面的保护层具有通过其形成的开口。 在该开口内形成一个支柱，并延伸至最上层保护层的至少一部分。 在最上保护层上延伸的部分呈现大致细长的形状。 在一个实施例中，开口相对于在最上保护层上延伸的凸起结构的部分的位置使得从开口的边缘到凸起的边缘的距离的比例大于或等于约 0.2。 在另一个实施例中，开口的位置相对于凸块的中心偏移。

公开(公告)号：US08922005B2

公开(公告)日：2014-12-30

申请号：US13444674

申请日：2012-04-11

申请人： Yen-Chang Hu ,  Ching-Wen Hsiao ,  Chih-Hua Chen ,  Chen-Shien Chen ,  Tin-Hao Kuo

发明人： Yen-Chang Hu ,  Ching-Wen Hsiao ,  Chih-Hua Chen ,  Chen-Shien Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： H01L25/50 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/81805

摘要： Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.

摘要翻译： 封装结构上的封装结构的方法和装置，其具有穿过通孔互连的凸块凸块。 一种结构包括具有多个通孔组件的互连层，每个穿孔组件包括至少一个柱形突起，其在导电垫上形成; 以及围绕所述通孔组件的密封剂，形成在所述密封剂的表面上并且连接到所述通孔组件和承载连接器的第一再分布层，以及在所述通孔组件的另一端处的互连层上的第二再分布层， 通过组件垂直延伸穿过互连层。 在一个实施例中，使用连接器将互连层安装到下封装衬底以形成封装结构上的封装。 第一集成电路器件可以安装在互连层的第二再分配层上。 公开了在封装结构上形成互连层和封装的方法。

公开(公告)号：US08318596B2

公开(公告)日：2012-11-27

申请号：US12704183

申请日：2010-02-11

申请人： Tin-Hao Kuo ,  Chen-Shien Chen ,  Ching-Wen Hsiao

发明人： Tin-Hao Kuo ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16507 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.

摘要翻译： 提供了一种用于半导体器件的导电柱。 导电柱形成为使得顶表面是非平坦的。 在实施例中，顶表面可以是凹形，凸形或波浪状。 可以在导电柱上形成可选的覆盖层，以允许更强的金属间化合物（IMC）层。 IMC层是在焊料材料和下层之间形成的层，例如导电柱或可选的封盖层。

公开(公告)号：US09449941B2

公开(公告)日：2016-09-20

申请号：US13178161

申请日：2011-07-07

申请人： Pei-Chun Tsai ,  Sheng-Yu Wu ,  Ching-Wen Hsiao ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Chung-Shi Liu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

发明人： Pei-Chun Tsai ,  Sheng-Yu Wu ,  Ching-Wen Hsiao ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Chung-Shi Liu ,  Chien-Hsiun Lee ,  Mirng-Ji Lii

IPC分类号： H01L29/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/48

摘要： A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections.

摘要翻译： 封装封装（PoP）包括具有多个衬底迹线的衬底，通过多个贴合在轨迹连接与衬底连接的衬底顶部的第一功能芯片，以及顶部上的第二功能芯片 的第一功能芯片，直接连接到基板。 另一个封装封装（PoP）包括：具有多个衬底迹线的衬底，通过在连接的SMD焊盘上形成的多个焊接掩模限定（SMD）连接到衬底的顶部上的第一功能芯片 焊料凸点，以及位于第一功能芯片顶部的第二功能芯片，通过多个贴合在线跟踪连接直接连接到基板。

公开(公告)号：US08664041B2

公开(公告)日：2014-03-04

申请号：US13445699

申请日：2012-04-12

申请人： Yu-Jen Tseng ,  Guan-Yu Chen ,  Sheng-Yu Wu ,  Chen-Hua Yu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Tin-Hao Kuo

发明人： Yu-Jen Tseng ,  Guan-Yu Chen ,  Sheng-Yu Wu ,  Chen-Hua Yu ,  Mirng-Ji Lii ,  Chen-Shien Chen ,  Tin-Hao Kuo

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： G06F17/5068 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81444 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2224/1144

摘要： A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.

摘要翻译： 一种用于防止在跟踪轨迹结构中的相邻金属迹线桥接的方法和装置。 一个实施例包括确定包装部件的热膨胀系数（CTE）和工艺参数。 然后分析设计参数，并且可以基于包装部件的CTE和工艺参数来修改设计参数。

公开(公告)号：US08598691B2

公开(公告)日：2013-12-03

申请号：US13228757

申请日：2011-09-09

申请人： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Ming-Da Cheng

发明人： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Ming-Da Cheng

IPC分类号： H01L23/695 ,  H01L29/40

CPC分类号： H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/13147 ,  H01L2224/141 ,  H01L2224/14136 ,  H01L2224/14145 ,  H01L2224/14156 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

摘要翻译： 公开了半导体器件及其制造和封装方法。 在一个实施例中，半导体器件包括集成电路和耦合到集成电路的表面的多个铜柱。 多个铜柱具有细长的形状。 多个铜柱的至少50％被布置成基本上向心的取向。

公开(公告)号：US20130270699A1

公开(公告)日：2013-10-17

申请号：US13449078

申请日：2012-04-17

申请人： Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Sheng-Yu Wu ,  Yao-Chun Chuang

发明人： Tin-Hao Kuo ,  Chen-Shien Chen ,  Mirng-Ji Lii ,  Chen-Hua Yu ,  Sheng-Yu Wu ,  Yao-Chun Chuang

IPC分类号： H01L23/498

CPC分类号： H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

摘要翻译： 提供了一种用于衬底的柱结构。 支柱结构可以具有一个或多个层，其中每个层可以具有圆锥形或球形。 在一个实施例中，柱结构用于跟踪跟踪（BOT）配置。 支柱结构在平面图中可以具有圆形或细长形状。 衬底可以耦合到另一衬底。 在一个实施例中，另一衬底可以具有凸起的导电迹线，柱结构可以联接到该导电迹线上。

公开(公告)号：US20130270682A1

公开(公告)日：2013-10-17

申请号：US13444674

申请日：2012-04-11

申请人： Yen-Chang Hu ,  Ching-Wen Hsiao ,  Chih-Hua Chen ,  Chen-Shien Chen ,  Tin-Hao Kuo

发明人： Yen-Chang Hu ,  Ching-Wen Hsiao ,  Chih-Hua Chen ,  Chen-Shien Chen ,  Tin-Hao Kuo

IPC分类号： H01L25/065 ,  H01L21/98

CPC分类号： H01L25/50 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/81805

摘要： Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.

公开(公告)号：US20110193220A1

公开(公告)日：2011-08-11

申请号：US12704183

申请日：2010-02-11

申请人： Tin-Hao Kuo ,  Chen-Shien Chen ,  Ching-Wen Hsiao

发明人： Tin-Hao Kuo ,  Chen-Shien Chen ,  Ching-Wen Hsiao

IPC分类号： H01L23/498 ,  H01L21/3205

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16507 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.

摘要翻译： 提供了一种用于半导体器件的导电柱。 导电柱形成为使得顶表面是非平面的。 在实施例中，顶表面可以是凹形，凸形或波浪状。 可以在导电柱上形成可选的覆盖层，以允许更强的金属间化合物（IMC）层。 IMC层是在焊料材料和下层之间形成的层，例如导电柱或可选的封盖层。

公开(公告)号：US08288871B1

公开(公告)日：2012-10-16

申请号：US13095185

申请日：2011-04-27

申请人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

发明人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.

摘要翻译： 凹凸跟踪（BOT）结构及其在芯片上的布局的实施例减少了金属焊盘上的电介质层和BOT结构的金属迹线上的应力。 通过将金属凸块的轴线定位成远离金属轨迹，可以减小应力，这可以降低金属迹线从基板和电介质层与金属垫分层的危险。 此外，金属焊盘和金属迹线上的电介质层的应力也可以通过将金属迹线的轴线朝向芯片的中心定向而减小。 结果，可以提高收率。