公开(公告)号：US09147585B2

公开(公告)日：2015-09-29

申请号：US14535591

申请日：2014-11-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/82 ,  H01L21/56 ,  H01L23/538 ,  H01L27/04 ,  H01L49/02 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US09099454B2

公开(公告)日：2015-08-04

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/36 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US20150041967A1

公开(公告)日：2015-02-12

申请号：US13964153

申请日：2013-08-12

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Veronika Huber ,  Thomas Kilger ,  Ralf Otremba ,  Bernd Stadler ,  Dominic Maier ,  Klaus Schiess ,  Andreas Schlögl ,  Uwe Wahl

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/561 ,  H01L21/568 ,  H01L23/36 ,  H01L23/49562 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L27/14618 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/85 ,  H01L2224/96 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00014

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract translation: 通过在模具的第一侧提供具有端子的半导体模具来制造半导体封装，在模具的相对的第二侧提供耦合到模具的材料，并将模具嵌入模制化合物中，使得模具被覆盖 通过除第一面以外的所有侧面的模塑料。 模塑料在靠近模具的第二侧的模塑料的一侧变细，以在模具的第二面露出材料，而不暴露模具的第二面。 在模具的第一侧上的端子形成电连接。 在晶体管管芯的情况下，端子可以是源极端子，并且晶体管管芯可以源极地附接到诸如引线框架的管芯焊盘的金属块。

公开(公告)号：US10930541B2

公开(公告)日：2021-02-23

申请号：US16249142

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Francesca Arcioni ,  Maciej Wojnowski

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.

公开(公告)号：US20180148322A1

公开(公告)日：2018-05-31

申请号：US15692938

申请日：2017-08-31

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Matthias Steiert ,  Chau Fatt Chiang ,  Christian Geissler ,  Bernd Goller ,  Thomas Kilger ,  Johannes Lodermeyer ,  Franz-Xaver Muehlbauer ,  Chee Yang Ng ,  Beng Keh See ,  Claus Waechter

IPC: B81B7/00 ,  B81C1/00

Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

公开(公告)号：US20170278836A1

公开(公告)日：2017-09-28

申请号：US15618684

申请日：2017-06-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger

IPC: H01L25/00 ,  H01F27/28 ,  H01F27/29 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H01L25/10 ,  H05K1/16 ,  H05K1/18

CPC classification number: H01L25/50 ,  H01F27/2804 ,  H01F27/29 ,  H01F2027/2809 ,  H01L21/32051 ,  H01L21/56 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/40 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/11005 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/40227 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83801 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/165 ,  H05K1/181 ,  H05K1/185 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

公开(公告)号：US09725303B1

公开(公告)日：2017-08-08

申请号：US15071882

申请日：2016-03-16

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Franz-Xaver Muehlbauer ,  Thomas Kilger

IPC: H01L21/50 ,  H01L23/49 ,  B81B7/00 ,  B81C1/00 ,  H04R19/00 ,  H04R1/28

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2207/012 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00301 ,  H04R1/086 ,  H04R1/28 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

Abstract: A semiconductor device includes a microelectromechanical system (MEMS) die, an encapsulation material, a via element, a non-conductive lid, and a conductive layer. The encapsulation material laterally surrounds the MEMS die. The via element extends through the encapsulation material. The non-conductive lid is over the MEMS die and defines a cavity. The conductive layer is over the MEMS die and the encapsulation material and is electrically coupled to the via element.

公开(公告)号：US09718678B2

公开(公告)日：2017-08-01

申请号：US14495920

申请日：2014-09-25

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Thomas Kilger

IPC: H01L23/02 ,  B81C1/00

CPC classification number: B81C1/00238 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/81

Abstract: According to various embodiments, a package arrangement may include: a first encapsulation material; at least one electronic circuit at least partially embedded in the first encapsulation material, the at least one electronic circuit including a first contact pad structure at a first side of the at least one electronic circuit; at least one electromechanical device disposed over the first side of the at least one electronic circuit, the at least one electromechanical device including a second contact pad structure facing the first side of the at least one electronic circuit; a redistribution layer structure between the at least one electromechanical device and the at least one electronic circuit, the redistribution layer structure electrically connecting the first contact pad structure with the second contact pad structure, wherein a gap is provided between the at least one electromechanical device and the redistribution layer structure; a second encapsulation material at least partially covering the at least one electromechanical device, wherein the gap is free of the second encapsulation material.

公开(公告)号：US09704843B2

公开(公告)日：2017-07-11

申请号：US14853808

申请日：2015-09-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger

IPC: H01L21/78 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/64 ,  H01L23/00 ,  H01F27/29 ,  H01L21/3205 ,  H01L25/065 ,  H01F27/28 ,  H05K1/16 ,  H05K1/18 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01F27/2804 ,  H01F27/29 ,  H01F2027/2809 ,  H01L21/32051 ,  H01L21/56 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/40 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/11005 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/40227 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83801 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/165 ,  H05K1/181 ,  H05K1/185 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

公开(公告)号：US09487392B2

公开(公告)日：2016-11-08

申请号：US14454247

申请日：2014-08-07

Applicant: Infineon Technologies AG

Inventor： Ulrich Wachter ,  Dominic Maier ,  Thomas Kilger

IPC: B81C1/00 ,  H01L23/48 ,  H01L23/00 ,  H01L23/552 ,  B81B7/00 ,  H01L21/56 ,  H03H9/10 ,  H04R19/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2201/0257 ,  H01L21/568 ,  H01L23/48 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H03H9/1064 ,  H04R19/005 ,  H01L2924/00

Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.

Abstract translation: 一种封装集成电路的方法包括：提供具有多个第一半导体管芯和多个第二半导体管芯的模制衬底，所述第二半导体管芯相互间隔开并被模制化合物覆盖。 将模塑料稀薄以暴露至少一些第二半导体管芯。 暴露的第二半导体管芯被移除以在模塑衬底中形成空腔。 多个第三半导体管芯被插入形成在模制基板中的空腔中，并且电连接形成于第一半导体管芯和第三半导体管芯。