公开(公告)号：US06297553B1

公开(公告)日：2001-10-02

申请号：US09422746

申请日：1999-10-22

申请人： Michio Horiuchi ,  Kazunari Imai

发明人： Michio Horiuchi ,  Kazunari Imai

IPC分类号： H01L2348

CPC分类号： H01L23/49827 ,  H01L23/3114 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3473 ,  H05K3/4038 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  H01L2224/05599

摘要： A semiconductor device that meets the demand for realizing semiconductor chips in small sizes. A semiconductor device in which connection lands 20 formed on the electrode terminal carrying surface of a semiconductor chip 10 are electrically connected, through connection bumps 14, to connection pads 22 formed on one surface of an interposing substrate 12 of an insulating material so as to face the connection lands 20, wherein conductor wiring patterns 24 inclusive of the connection pads 22 are formed on one surface of the interposing substrate 12, conductor wiring patterns 30 inclusive of terminal lands on where the external connection terminals 26 will be mounted, are formed on the other surface of the interposing substrate 12, and the conductor wiring patterns 24 formed on one surface of the interposing substrate 12 are connected to the conductor wiring patterns 30 formed on the other surface of the interposing substrate 12 through vias 32 formed by filling recesses with a metal by plating, the recesses being formed to penetrate through the insulating material of the interposing substrate 12 and permitting the back surfaces of the conductor wiring patterns 24 on the side of the insulating material to be exposed on the bottom surfaces thereof.

摘要翻译： 一种满足小尺寸半导体芯片实现需求的半导体器件。 形成在半导体芯片10的电极端子承载表面上的连接焊盘20通过连接凸块14电连接到形成在绝缘材料的插入基板12的一个表面上的连接焊盘22的半导体器件， 连接焊盘20，其中包括连接焊盘22的导体布线图案24形成在插入基板12的一个表面上，导体布线图案30包括将安装外部连接端子26的端子焊盘的导体布线图案30形成在 插入基板12的另一个表面和形成在插入基板12的一个表面上的导体布线图案24通过通孔32连接到形成在插入基板12的另一个表面上的导体布线图案30， 通过电镀形成金属，所述凹部形成为穿透插入物的绝缘材料 g基板12，并且使绝缘材料侧的导体布线图案24的背面露出在其底面上。

公开(公告)号：US06271478B1

公开(公告)日：2001-08-07

申请号：US09195831

申请日：1998-11-19

申请人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Chiaki Takubo

发明人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Chiaki Takubo

IPC分类号： H05K114

CPC分类号： H05K1/112 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/10734

摘要： A multi-layer circuit board having a decreased number of circuit boards for mounting an electronic part that has connection electrodes arranged in the form of an area array, featuring a high yield and improved reliability. In the multi-layer circuit board, circuit patterns formed on a first circuit board on the surface of the side where said electronic part is mounted, are connected to every land positioned on the outermost side of the lands arranged in the form of an area array, and are connected to the lands alternatingly selected from the lands of the second sequence and the third sequence of the inner side; circuit patterns formed on a second circuit board are connected to every via electrically connected to the lands of the second sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the fourth sequence and the fifth sequence on the first circuit board; circuit patterns formed on a third circuit board are connected to every via electrically connected to the lands of the third sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the sixth sequence and the seventh sequence on the first circuit board; and circuit patterns formed on a fourth circuit board are connected to every via electrically connected to the lands of the eighth sequence and the ninth sequence on the first circuit board.

摘要翻译： 一种多层电路板，其具有用于安装具有以区域阵列形式布置的连接电极的电子部件的电路板数量减少，具有高产量和改善的可靠性。 在多层电路板中，形成在安装有所述电子部件的一侧的表面上的第一电路板上的电路图案连接到位于以区域阵列形式布置的焊盘的最外侧的每个区域 并且连接到从第二序列的焊盘和内侧的第三序列交替地选择的焊盘; 形成在第二电路板上的电路图案连接到电连接到第一电路板上未连接电路图案的第二序列的焊盘的每个通孔，以及电连接到第四电路板的所有焊盘的通孔 序列和第一个电路板上的第五个序列; 形成在第三电路板上的电路图案连接到电连接到第一电路板上未连接电路图案的第三序列的焊盘的每个通孔，以及电连接到第六电路板的所有焊盘的通孔 序列和第七个序列在第一个电路板上; 并且形成在第四电路板上的电路图案连接到电连接到第一电路板上的第八序列和第九序列的焊盘的每个通孔。

公开(公告)号：US06093476A

公开(公告)日：2000-07-25

申请号：US71875

申请日：1998-05-01

申请人： Michio Horiuchi ,  Yukiharu Takeuchi

发明人： Michio Horiuchi ,  Yukiharu Takeuchi

IPC分类号： H05K1/02 ,  H01L21/48 ,  H01L23/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498 ,  H05K1/00 ,  B32B3/06

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/13 ,  H01L23/15 ,  H05K1/0287 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32188 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A wiring substrate is provided in which a common core member is used and the cost can be reduced. Diameters of the penetrating filled vias (18) are the same and not more than 300 .mu.m, and the penetrating filled vias (18) are formed on a core substrate (20) into a matrix-shape at regular intervals of not more than 2 mm. On the surface of the core substrate (20), a plane wiring pattern (17) is formed through an insulating layer (16). Each pad portion on the wiring pattern (17) is electrically connected with each corresponding via of the filled vias (18) by one to one through a connecting via (28) which penetrates the insulating layer (16), and some of the filled vias (18) are not connected with the wiring pattern (17).

摘要翻译： 提供一种布线基板，其中使用共同的芯构件并且可以降低成本。 穿透填充过孔（18）的直径相同且不大于300μm，并且穿透填充的通孔（18）以不大于2的规则间隔在芯基板（20）上形成矩阵形状 mm。 在芯基板（20）的表面上，通过绝缘层（16）形成平面布线图案（17）。 布线图案（17）上的每个焊盘部分通过穿过绝缘层（16）的连接通孔（28）与填充的通孔（18）的每个相应的通孔电连接一个一个，并且一些填充的通孔 （18）不与布线图案17连接。

公开(公告)号：US5737191A

公开(公告)日：1998-04-07

申请号：US628346

申请日：1996-04-05

申请人： Michio Horiuchi ,  Yoichi Harayama

发明人： Michio Horiuchi ,  Yoichi Harayama

IPC分类号： H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H05K7/02

CPC分类号： H01L23/3675 ,  H01L21/563 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/3164 ,  H01L23/49816 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/83951 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/15787

摘要： A semiconductor chip mount structure includes a substrate having a base surface on which base side connectors are formed; a semiconductor chip mounted on the base surface, the semiconductor chip having chip side connectors on a first surface thereof facing the base surface, the chip side connectors being electrically connected to the base side connectors; an insulating resin layer covering the chip side connectors and the base side connectors; a metal layer, made of a metal having a melting point lower than a temperature at which the electrical components of the semiconductor chip may be thermally destroyed, for covering the semiconductor chip and the insulating resin layer; and a wetting characteristic improving layer such as a metal powder or foil layer, formed along a contact surface between the metal layer and the insulation resin layer.

摘要翻译： 一种半导体芯片安装结构，包括具有形成有基极侧连接器的基面的基板; 半导体芯片安装在基底表面上，半导体芯片在其第一表面上具有面向基面的芯片侧连接器，芯片侧连接器电连接到基座侧连接器; 覆盖芯片侧连接器和基座侧连接器的绝缘树脂层; 金属层，其熔点低于半导体芯片的电气部件可能被热破坏的温度的金属制成，用于覆盖半导体芯片和绝缘树脂层; 以及沿金属层和绝缘树脂层之间的接触面形成的润湿特性改善层，例如金属粉末或箔层。

公开(公告)号：US5683791A

公开(公告)日：1997-11-04

申请号：US689692

申请日：1996-08-13

申请人： Michio Horiuchi ,  Yoichi Harayama

发明人： Michio Horiuchi ,  Yoichi Harayama

IPC分类号： H05K1/03 ,  B32B37/18 ,  H01L21/48 ,  H05K1/09 ,  H05K3/12 ,  H05K3/24 ,  H05K3/26 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00 ,  B32B15/00

CPC分类号： B32B37/18 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/092 ,  H05K3/4061 ,  H05K1/0306 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1383 ,  H05K3/245 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T156/10 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/252

摘要： Internal wiring made of copper of low-resistance is provided in a ceramic oxide. Green sheets 10 made of oxide powder are provided with plane wiring 18 and/or via wiring 14 in which copper is used as wiring material. The green sheets 10 are laminated and integrated in such a manner that the wiring portions 4 and 18 are covered with the green sheet so as not to be exposed onto a surface. Then the laminated body is fired at a maximum temperature in a range from 1,083.degree. to 1,800.degree. C.

摘要翻译： 在陶瓷氧化物中设置由低电阻铜制成的内部布线。 由氧化物粉末制成的生片10具有平面布线18和/或通过其中使用铜作为布线材料的布线14。 生片10以这样的方式层叠并整合，使得布线部分4和18被生片覆盖，以便不暴露在表面上。 然后将层压体在最高温度为1083℃至1800℃的范围内烧制。

公开(公告)号：US08877454B2

公开(公告)日：2014-11-04

申请号：US12681573

申请日：2008-10-03

申请人： Shinichiro Nishimura ,  Yasuro Shinohara ,  Yoshiaki Miura ,  Hiroshi Yamazaki ,  Michio Horiuchi ,  Hiroaki Motoki ,  Toshiharu Kuroda ,  Yoko Kita ,  Mika Nakano

发明人： Shinichiro Nishimura ,  Yasuro Shinohara ,  Yoshiaki Miura ,  Hiroshi Yamazaki ,  Michio Horiuchi ,  Hiroaki Motoki ,  Toshiharu Kuroda ,  Yoko Kita ,  Mika Nakano

IPC分类号： C12Q1/37 ,  G01N33/68 ,  G01N30/72 ,  H01J49/00

CPC分类号： G01N33/6848 ,  G01N30/7233 ,  G01N2400/00 ,  H01J49/00

摘要： To provide an autoanalyzer for analyzing a sugar chain contained in a biological sample, in particular, serum. Namely, it is intended to provide a method of analyzing a sugar chain in a sample, which comprises the following steps: A) the sugar chain-releasing step of releasing the sugar chain in the sample; B) the detection sample-preparing step of preparing the released sugar chain for detection; and, in the case of conducting mass spectrometry using a plate, C) the step of forming a plate for the mass spectrometry having the captured sugar chain dotted thereon which comprises the step of providing the tagged sugar chain sample solution obtained in the step B) on a collection plate; and, if required, the step of conducting an operation in a solid phase support-enclosed plate to form the plate for mass spectrometry; and D) the step of analyzing the sugar chain to be assayed.

摘要翻译： 提供一种用于分析生物样品，特别是血清中所含的糖链的自动分析仪。 即，提供一种分析样品中的糖链的方法，其包括以下步骤：A）释放样品中的糖链的糖链释放步骤; B）制备释放的糖链进行检测的检测样品制备步骤; 并且在使用板进行质谱分析的情况下，C）形成具有点状捕获的糖链的用于质谱的板的步骤，其包括提供步骤B）中获得的标记的糖链样品溶液的步骤， 在收集板上; 如果需要，在固相支持封闭板中进行操作以形成质谱板的步骤; 和D）分析要测定的糖链的步骤。

公开(公告)号：US20120327626A1

公开(公告)日：2012-12-27

申请号：US13528987

申请日：2012-06-21

申请人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki

发明人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki

IPC分类号： H05K1/02 ,  H05K3/00 ,  H05K7/06

CPC分类号： H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/10378 ,  Y10T29/49124 ,  H01L2924/00

摘要： One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.

摘要翻译： 一个实施例提供一种布线基板，包括：具有绝缘基底构件的芯基板，所述绝缘基底构件具有第一表面和第二表面;多个线状导体，从所述第一表面穿过所述绝缘基底构件到所述第二表面; 连接到所述绝缘基体的第一表面和所述第二表面中的至少一个的无机材料层; 以及穿透无机材料层的穿透线，其中穿透线的一端电连接到线性导体的相应部分，而不会发生凹凸。

公开(公告)号：US08138609B2

公开(公告)日：2012-03-20

申请号：US12832177

申请日：2010-07-08

申请人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

发明人： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC分类号： H01L23/48

CPC分类号： H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

摘要： In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

摘要翻译： 在半导体器件中，衬底包括从衬底的顶表面到底表面穿透衬底的多个线导体。 半导体芯片固定在基板的孔中。 在衬底和半导体芯片的顶表面上形成第一绝缘层。 第一布线层形成在第一绝缘层上，并且经由第一绝缘层的通孔与半导体芯片电连接，一些线导体暴露于一个通孔。 在基板和半导体芯片的底面上形成第二绝缘层。 第二布线层形成在第二绝缘层上，并且经由第二绝缘层的通孔与暴露于通孔的一些线导体电连接。

公开(公告)号：US20110111443A1

公开(公告)日：2011-05-12

申请号：US12681573

申请日：2008-10-03

申请人： Shinichiro Nishimura ,  Yasuro Shinohara ,  Yoshiaki Miura ,  Hiroshi Yamazaki ,  Michio Horiuchi ,  Hiroaki Motoki ,  Toshiharu Kuroda ,  Yoko Kita ,  Mika Nakano

发明人： Shinichiro Nishimura ,  Yasuro Shinohara ,  Yoshiaki Miura ,  Hiroshi Yamazaki ,  Michio Horiuchi ,  Hiroaki Motoki ,  Toshiharu Kuroda ,  Yoko Kita ,  Mika Nakano

IPC分类号： C12Q1/37 ,  C12M1/34 ,  C12P19/00 ,  C40B60/14

CPC分类号： G01N33/6848 ,  G01N30/7233 ,  G01N2400/00 ,  H01J49/00

摘要： To provide an autoanalyzer for analyzing a sugar chain contained in a biological sample, in particular, serum. Namely, it is intended to provide a method of analyzing a sugar chain in a sample, which comprises the following steps: A) the sugar chain-releasing step of releasing the sugar chain in the sample; B) the detection sample-preparing step of preparing the released sugar chain for detection; and, in the case of conducting mass spectrometry using a plate, C) the step of forming a plate for the mass spectrometry having the captured sugar chain dotted thereon which comprises the step of providing the tagged sugar chain sample solution obtained in the step B) on a collection plate; and, if required, the step of conducting an operation in a solid phase support-enclosed plate to form the plate for mass spectrometry; and D) the step of analyzing the sugar chain to be assayed.

摘要翻译： 提供一种用于分析生物样品，特别是血清中所含的糖链的自动分析仪。 即，提供一种分析样品中的糖链的方法，其包括以下步骤：A）释放样品中的糖链的糖链释放步骤; B）制备释放的糖链进行检测的检测样品制备步骤; 并且在使用板进行质谱分析的情况下，C）形成具有点状捕获的糖链的用于质谱的板的步骤，其包括提供步骤B）中获得的标记的糖链样品溶液的步骤， 在收集板上; 如果需要，在固相支持封闭板中进行操作以形成质谱板的步骤; 和D）分析要测定的糖链的步骤。

公开(公告)号：US07803491B2

公开(公告)日：2010-09-28

申请号：US11125064

申请日：2005-05-09

申请人： Michio Horiuchi ,  Shigeaki Suganuma ,  Misa Watanabe ,  Yasue Tokutake

发明人： Michio Horiuchi ,  Shigeaki Suganuma ,  Misa Watanabe ,  Yasue Tokutake

IPC分类号： H01M8/22 ,  H01M8/24

CPC分类号： H01M8/0256 ,  H01M8/006 ,  H01M8/1097 ,  H01M8/1226 ,  H01M8/1286 ,  H01M8/2425 ,  H01M8/2432 ,  H01M8/2465 ,  H01M2008/1293 ,  H01M2250/30 ,  Y02B90/18

摘要： A solid electrolyte fuel cell configuration provided with a single sheet shaped solid electrolyte substrate formed with a plurality of fuel cells and thereby not having a sealed structure, achieving a reduction of the size and a reduction of the cost, and able to improve the durability and improve the power generation efficiency, a single sheet shaped solid electrolyte substrate, in particular a solid electrolyte fuel cell configuration provided with a single sheet shaped solid electrolyte substrate, a plurality of anode layers formed on one side of the solid electrolyte substrate, and a plurality of cathode layers formed on the side opposite to the one side of the solid electrolyte substrate at positions facing the anode layers, the anode layers and cathode layers facing each other across the solid electrolyte substrate forming a plurality of fuel cells, the anode layers and cathode layers being connected in series.

摘要翻译： 一种固体电解质燃料电池结构，其具有形成有多个燃料电池的单片状固体电解质基板，由此不具有密封结构，实现了尺寸的减小和成本的降低，并且能够提高耐久性和 提高发电效率，单片状固体电解质基板，特别是设置有单片状固体电解质基板的固体电解质型燃料电池结构体，形成在固体电解质基板一侧的多个阳极层，以及多个 在与固体电解质基板的一侧相对的一侧形成的阴极层的面对阳极层的位置，阳极层和阴极层在形成多个燃料电池的固体电解质基板上彼此面对，阳极层和阴极 层串联连接。