公开(公告)号：US4048356A

公开(公告)日：1977-09-13

申请号：US640511

申请日：1975-12-15

申请人： Peter Bakos ,  Irving Memis ,  John Rasile

发明人： Peter Bakos ,  Irving Memis ,  John Rasile

IPC分类号： H05K5/00 ,  C09D4/00 ,  H01L21/312 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H05K3/28 ,  H05K5/06 ,  B05D3/02 ,  B05D7/26

CPC分类号： H01L23/296 ,  C09D4/00 ,  H01L21/56 ,  H01L2924/0002 ,  H05K3/285 ,  Y10S428/901 ,  Y10T428/31507 ,  Y10T428/31529 ,  Y10T428/31663 ,  Y10T428/31678 ,  Y10T428/31681 ,  Y10T428/31688 ,  Y10T428/31692 ,  Y10T428/31696 ,  Y10T428/31699

摘要： A hermetic topsealant for metal electrodes on components and other microelectronic circuitry is formed by polymerizing a mixture of an unsaturated silane monomer, a bifunctional silane adhesion promoter, a polymeric plasticizer and a stabilizer.The purpose of this abstract is to enable the public and the Patent Office to rapidly determine the subject matter of the technical disclosure of the application. This abstract is neither intended to define the invention of the application nor is it intended to be limiting as to the scope thereof.

摘要翻译： 通过聚合不饱和硅烷单体，双功能硅烷粘合促进剂，聚合物增塑剂和稳定剂的混合物，形成用于组件和其它微电子电路上的金属电极的气密性顶层。

公开(公告)号：US07470990B2

公开(公告)日：2008-12-30

申请号：US11086323

申请日：2005-03-23

申请人： Robert M. Japp ,  Irving Memis ,  Kostas I. Papathomas

发明人： Robert M. Japp ,  Irving Memis ,  Kostas I. Papathomas

IPC分类号： H01L23/52

CPC分类号： H01L23/3735 ,  H01L23/145 ,  H01L23/3733 ,  H01L23/4922 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/564 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/4602 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/0278 ,  H05K2201/068

摘要： A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

摘要翻译： 一种电路化基板，包括复合层，所述复合层包括第一介电子层，所述第一介电子层包括具有低热膨胀系数的多个纤维和低吸湿性树脂的第二介电子层，所述第二介电子层不包括连续的或 半连续纤维等作为其一部分。 衬底还包括至少一个作为其一部分的导电层。 还提供电气组件和制造基板的方法，如本发明的电路化基板作为其一部分的信息处理系统（例如，计算机）。

公开(公告)号：US20080308923A1

公开(公告)日：2008-12-18

申请号：US12186767

申请日：2008-08-06

申请人： Jean Audet ,  Irving Memis

发明人： Jean Audet ,  Irving Memis

IPC分类号： H01L23/485

CPC分类号： H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

摘要： A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

摘要翻译： 一种多层芯片载体，增加了配电PTH的空间，降低了功率相关噪声。 在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层附近的边缘信号焊盘逸出外，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层，剩余的信号垫再次移动，更靠近芯片占位面的边缘。 在第二扇出层中，电压层以下，剩余的信号垫排出。 信号垫移动的区域为功率PTH提供了增加的空间。

公开(公告)号：US20060012054A1

公开(公告)日：2006-01-19

申请号：US11233572

申请日：2005-09-23

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H01L23/48

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

摘要： The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip through the core to the bottom surface where signals exit the carrier to the printed wiring board, which is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip, thereby increasing the density of circuits escaping the footprint area.

摘要翻译： 通过将来自芯片的信号重新定位到载体的上部信号层，可以改善信号从倒装芯片/球栅阵列组件中的半导体芯片到印刷线路板的逸出。 这涉及通过芯片载体将电路线从通过芯到芯片的芯片通过芯片的顶表面扇出，信号从载体离开印刷电路板，这是通过更好地利用表面积来实现的 核心和芯片之间的信号平面。 信号在每个顶部信号平面上被扇出，使得更多的信号通过芯中的通孔传输到底部信号平面，在那里它们可以逃逸到芯片的覆盖区域之外，从而增加了 电路逃离占地面积。

公开(公告)号：US06965170B2

公开(公告)日：2005-11-15

申请号：US10715690

申请日：2003-11-18

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

摘要： The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip, through the core to the bottom surface where signals exit the carrier to the printed wiring board. This fanning out is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip thereby increasing the density of circuits escaping the footprint area.

摘要翻译： 通过将来自芯片的信号重新定位到载体的上部信号层，可以改善信号从倒装芯片/球栅阵列组件中的半导体芯片到印刷线路板的逸出。 这涉及从穿过芯片的顶表面通过芯片载体扇出电路线，通过芯到底表面，其中信号从载体离开印刷线路板。 通过更好地利用芯和芯片之间的信号平面的表面积来实现扇形化。 信号在每个顶部信号平面上扇出，使得更多的信号通过芯中的通孔传输到底部信号平面，在那里它们可以逃离到芯片的覆盖区域外部，从而增加电路的密度 逃离足迹区域。

公开(公告)号：US20050104221A1

公开(公告)日：2005-05-19

申请号：US10715690

申请日：2003-11-18

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

摘要： The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip, through the core to the bottom surface where signals exit the carrier to the printed wiring board. This fanning out is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip thereby increasing the density of circuits escaping the footprint area.

公开(公告)号：US20050093133A1

公开(公告)日：2005-05-05

申请号：US10701311

申请日：2003-11-04

申请人： Kazushige Kawasaki ,  Irving Memis

发明人： Kazushige Kawasaki ,  Irving Memis

IPC分类号： H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H01L29/40

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/029 ,  H05K2201/09609 ,  H05K2201/09627

摘要： The density of plated thru holes in a glass fiber based chip carrier is increased by off-setting holes to positions in which fibers from adjacent holes will not connect. Elongated strip zones or regions having a width approximately the diameter of the holes and running along orthogonal columns and rows of holes, parallel to the direction of fibers, define regions of fibers that can possibly cause shorting between holes. Rotating a conventional X-Y grid pattern of equidistant holes so as to position, for example, alternate holes in one direction between the elongated strip zones running in the opposite direction significantly increases the distance between holes along the elongated strip zones running in each direction. The holes are positioned between elongated strip zones with sufficient clearance to compensate for variations in the linear path of fibers.

摘要翻译： 基于玻璃纤维的芯片载体中的电镀通孔的密度通过偏移孔增加到相邻孔的纤维将不连接的位置。 宽度大约为孔的宽度的区域或区域平行于纤维方向的正交列和孔排沿着孔的直径延伸，限定了可能导致孔之间短路的纤维区域。 旋转等距孔的常规X-Y网格图案，以便例如在沿相反方向运行的细长条带之间的一个方向上的交替孔定位显着地增加沿着沿每个方向运行的细长条带的孔之间的距离。 孔位于具有足够间隙的细长带区之间以补偿纤维线性路径的变化。

公开(公告)号：US06418616B2

公开(公告)日：2002-07-16

申请号：US09795852

申请日：2001-02-28

申请人： Anilkumar C. Bhatt ,  Voya R. Markovich ,  Irving Memis ,  William E. Wilson

发明人： Anilkumar C. Bhatt ,  Voya R. Markovich ,  Irving Memis ,  William E. Wilson

IPC分类号： H01K310

CPC分类号： H05K3/0094 ,  B32B7/04 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/184 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0353 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

摘要翻译： 一种方法提供在具有填充的电镀通孔的子复合材料上的添加电镀。 在电穿孔和填充通孔之后，通过无电沉积实现细线电路。 精细线路电路可以通过无地电镀通孔，从而增加纵横比和用于附加部件和布线的可用表面积。

公开(公告)号：US6069023A

公开(公告)日：2000-05-30

申请号：US94401

申请日：1998-06-10

申请人： William Emmett Bernier ,  Michael Anthony Gaynes ,  Irving Memis ,  Hussain Shaukatuallah

发明人： William Emmett Bernier ,  Michael Anthony Gaynes ,  Irving Memis ,  Hussain Shaukatuallah

IPC分类号： H01L23/373 ,  H01L21/44 ,  H01L21/52 ,  H01L21/56 ,  H01L21/60 ,  H01L23/34 ,  H01L23/367 ,  H01L23/433

CPC分类号： H01L24/31 ,  H01L21/563 ,  H01L23/367 ,  H01L23/433 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/3025

摘要： An aluminum or copper heat sink is attached to a ceramic cap or exposed semiconductor chip using an adhesive of silicon or flexible-epoxy adhesive. The aluminum may be coated by anodizing or Chromate conversion or the copper may be coated with nickel or gold Chromium. Such structures are especially useful for flip chip attachment to flexible or rigid organic circuit boards or modules such as CQFP, CBGA, CCGA, CPGA, TBGA, PBGA, DCAM, MCM-L, and other chip carrier packages in which the back side of chips are connected directly to heat sinks. These adhesive materials withstand wet or dry thermal cycle tests of -65 to 150.degree. C. for 1,000 cycles and 85.degree. C. and 85% relative humidity for 1000 hours while maintaining a tensile strenth of at least 500 psi. The adhesive contains materials having high thermal conductivity and a low coefficient of thermal expansion (CTE) in order to provide increased thermal performance and a CTE between that of the silicon metal die and the metal of the heat sink.

摘要翻译： 使用硅或柔性环氧树脂粘合剂的粘合剂将铝或铜散热器附接到陶瓷帽或裸露的半导体芯片。 可以通过阳极氧化或铬酸盐转化来涂覆铝，或者铜可以用镍或金铬镀覆。 这种结构对于倒装芯片连接到诸如CQFP，CBGA，CCGA，CPGA，TBGA，PBGA，DCAM，MCM-L和其他芯片载体封装的柔性或刚性有机电路板或模块特别有用，其中芯片的背面 直接连接到散热片。 这些粘合剂材料经受湿度或干热循环试验，在-65至150℃下进行1000次循环，85℃和85％相对湿度下持续1000小时，同时保持至少500psi的拉伸强度。 粘合剂包含具有高导热性和低热膨胀系数（CTE）的材料，以便提供增加的热性能和在硅金属模具和散热器的金属之间的CTE。

公开(公告)号：US07454833B2

公开(公告)日：2008-11-25

申请号：US11651631

申请日：2007-01-09

申请人： Jean Audet ,  Irving Memis

发明人： Jean Audet ,  Irving Memis

IPC分类号： H05K3/00 ,  H05K3/10

CPC分类号： H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

摘要： A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

摘要翻译： 一种多层芯片载体，增加了配电PTH的空间，降低了功率相关噪声。 在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层附近的边缘信号焊盘逸出，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层，剩余的信号垫再次移动，更靠近芯片占位面的边缘。 在第二扇出层中，电压层以下，剩余的信号垫排出。 信号垫移动的区域为功率PTH提供了增加的空间。