公开(公告)号：US4048356A

公开(公告)日：1977-09-13

申请号：US640511

申请日：1975-12-15

申请人： Peter Bakos ,  Irving Memis ,  John Rasile

发明人： Peter Bakos ,  Irving Memis ,  John Rasile

IPC分类号： H05K5/00 ,  C09D4/00 ,  H01L21/312 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H05K3/28 ,  H05K5/06 ,  B05D3/02 ,  B05D7/26

CPC分类号： H01L23/296 ,  C09D4/00 ,  H01L21/56 ,  H01L2924/0002 ,  H05K3/285 ,  Y10S428/901 ,  Y10T428/31507 ,  Y10T428/31529 ,  Y10T428/31663 ,  Y10T428/31678 ,  Y10T428/31681 ,  Y10T428/31688 ,  Y10T428/31692 ,  Y10T428/31696 ,  Y10T428/31699

摘要： A hermetic topsealant for metal electrodes on components and other microelectronic circuitry is formed by polymerizing a mixture of an unsaturated silane monomer, a bifunctional silane adhesion promoter, a polymeric plasticizer and a stabilizer.The purpose of this abstract is to enable the public and the Patent Office to rapidly determine the subject matter of the technical disclosure of the application. This abstract is neither intended to define the invention of the application nor is it intended to be limiting as to the scope thereof.

摘要翻译： 通过聚合不饱和硅烷单体，双功能硅烷粘合促进剂，聚合物增塑剂和稳定剂的混合物，形成用于组件和其它微电子电路上的金属电极的气密性顶层。

公开(公告)号：US20100060381A1

公开(公告)日：2010-03-11

申请号：US12283146

申请日：2008-09-09

申请人： Rabindra N. Das ,  John M. Lauffer ,  Irving Memis ,  Steven G. Rosser

发明人： Rabindra N. Das ,  John M. Lauffer ,  Irving Memis ,  Steven G. Rosser

IPC分类号： H03H7/00 ,  H05K3/30

CPC分类号： H05K1/162 ,  H05K1/023 ,  H05K1/0234 ,  H05K1/167 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/0361 ,  Y10T29/4913 ,  Y10T428/12493 ,  Y10T428/24917 ,  Y10T428/31511

摘要： A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

摘要翻译： 多层嵌入式电容和电阻基板芯。 提供至少一层电阻材料。 电阻材料层具有嵌入其中的导电材料层。 在电阻材料层上设置至少一层高介电常数的电容材料层。 通孔由激光形成。

公开(公告)号：US07622384B2

公开(公告)日：2009-11-24

申请号：US12003299

申请日：2007-12-21

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H01L21/60 ,  H01L21/441

CPC分类号： H05K1/181 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0248 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

摘要： A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. The method involves forming the line patterns in such a manner so as to reduce line skew.

摘要翻译： 一种制造电子封装的方法，该电子封装包括其上定位有至少两个电气部件的电路化基板。 该包装包括接触部位的图案，每个接触部位具有与其耦合的部件之一。 接触部位的图案依次通过一组导线相互电连接，导线基本上防止偏斜具有基本上相同的长度。 该方法包括以这样的方式形成线图案以便减少线偏移。

公开(公告)号：US20060255460A1

公开(公告)日：2006-11-16

申请号：US11127160

申请日：2005-05-12

申请人： Irving Memis

发明人： Irving Memis

IPC分类号： H01L23/48

CPC分类号： H05K1/181 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0248 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

摘要： An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.

摘要翻译： 一种电子封装，其包括具有定位在其上的至少两个电气部件的电路化基板。 该包装包括接触部位的图案，每个接触部位具有与其耦合的部件之一。 接触部位的图案依次通过一组导线相互电连接，导线基本上防止偏斜具有基本上相同的长度。 还提供了制造包装的方法，电路化基板和信息处理系统也是如此，后者适于将一个或多个电子包装作为其一部分。

公开(公告)号：US07067916B2

公开(公告)日：2006-06-27

申请号：US09885853

申请日：2001-06-20

申请人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

发明人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/351 ,  H05K3/3436 ,  H01L2924/00

摘要： A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.

公开(公告)号：US20060065433A1

公开(公告)日：2006-03-30

申请号：US10953923

申请日：2004-09-29

申请人： Charles Danoski ,  Irving Memis ,  Steven Rosser

发明人： Charles Danoski ,  Irving Memis ,  Steven Rosser

IPC分类号： H05K7/06

CPC分类号： H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09663 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

摘要： A circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer. A method of making the substrate, and an electrical assembly and information handling system (e.g., computer) utilizing the substrate are also disclosed.

摘要翻译： 电路化基板被设计为基本上消除信号通过基板电路的信号线时的阻抗中断。 衬底包括具有多个导体的第一导电层，电组件可以在其上定位和电耦合。 这些焊盘在衬底内进一步耦合到信号线（例如，使用通孔），并且这些信号线还被进一步耦合到位于衬底内的另外多个导电衬垫。 信号线被定位成位于衬底的第一导电层和位于包括信号线的第二导电层下面的第三导电层内的电压平面之间。 可以在第三导电层的第一电压平面附近使用第二电压平面。 通孔也可用于将耦合到第一导体的信号线耦合到形成第三导电层的一部分的第二多个导体。 还公开了制造衬底的方法，以及利用衬底的电组件和信息处理系统（例如，计算机）。

公开(公告)号：US06251707B1

公开(公告)日：2001-06-26

申请号：US09546567

申请日：2000-04-11

申请人： William Emmett Bernier ,  Michael Anthony Gaynes ,  Irving Memis ,  Hussain Shaukatuallah

发明人： William Emmett Bernier ,  Michael Anthony Gaynes ,  Irving Memis ,  Hussain Shaukatuallah

IPC分类号： H01L2144

CPC分类号： H01L24/31 ,  H01L21/563 ,  H01L23/367 ,  H01L23/433 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83951 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/00012

摘要： An aluminum or copper heat sink is attached to a ceramic cap or exposed semiconductor chip using an adhesive of silicone or flexible-epoxy adhesive. The aluminum may be coated by anodizing or chromate conversion or the copper may be coated with nickel or gold or chromium. Such structures are especially useful for flip chip attachment to flexible or rigid organic circuit boards or modules such as CQFP, CBGA, CCGA, CPGA, TBGA, PEGA, DCAM, MCM-L, and other chip carrier packages in which the back side of chips are connected directly to heat sinks. These adhesive materials withstand wet or dry thermal cycle tests of −65 to 1500° C. for 1,000 cycles and 85° C. and 85% relative humidity for 1000 hours while maintaining a tensile strenth of at least 500 psi. The adhesive contains materials having high thermal conductivity and a low coefficient of thermal expansion (CTE) in order to provide increased thermal performance.

摘要翻译： 使用硅树脂或柔性环氧树脂粘合剂的粘合剂将铝或铜散热器连接到陶瓷帽或裸露的半导体芯片。 可以通过阳极氧化或铬酸盐转化来涂覆铝，或者铜可以用镍或金或铬涂覆。 这种结构对于倒装芯片连接到诸如CQFP，CBGA，CCGA，CPGA，TBGA，PEGA，DCAM，MCM-L和其它芯片载体封装的柔性或刚性有机电路板或模块特别有用，其中芯片的背面 直接连接到散热片。 这些粘合剂材料可承受-65至1500℃，1000次循环，85℃和85％相对湿度下持续1000小时的湿循环或干热循环试验，同时保持至少500psi的拉伸强度。 粘合剂含有具有高导热性和低热膨胀系数（CTE）的材料，以提供增加的热性能。

公开(公告)号：US06195883B1

公开(公告)日：2001-03-06

申请号：US09047984

申请日：1998-03-25

申请人： Anilkumar C. Bhatt ,  Voya R. Markovich ,  Irving Memis ,  William E. Wilson

发明人： Anilkumar C. Bhatt ,  Voya R. Markovich ,  Irving Memis ,  William E. Wilson

IPC分类号： H01K310

CPC分类号： H05K3/0094 ,  B32B7/04 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/184 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0353 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

摘要翻译： 一种方法提供在具有填充的电镀通孔的子复合材料上的添加电镀。 在电穿孔和填充通孔之后，通过无电沉积实现细线电路。 精细线路电路可以通过无地电镀通孔，从而增加纵横比和用于附加部件和布线的可用表面积。

公开(公告)号：US07791897B2

公开(公告)日：2010-09-07

申请号：US12283146

申请日：2008-09-09

申请人： Rabindra N. Das ,  John M. Lauffer ,  Irving Memis ,  Steven G. Rosser

发明人： Rabindra N. Das ,  John M. Lauffer ,  Irving Memis ,  Steven G. Rosser

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H05K1/023 ,  H05K1/0234 ,  H05K1/167 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/0361 ,  Y10T29/4913 ,  Y10T428/12493 ,  Y10T428/24917 ,  Y10T428/31511

摘要： A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

摘要翻译： 多层嵌入式电容和电阻基板芯。 提供至少一层电阻材料。 电阻材料层具有嵌入其中的导电材料层。 在电阻材料层上设置至少一层高介电常数的电容材料层。 通孔由激光形成。

公开(公告)号：US20080296054A1

公开(公告)日：2008-12-04

申请号：US12164478

申请日：2008-06-30

申请人： Jean Audet ,  Irving Memis

发明人： Jean Audet ,  Irving Memis

IPC分类号： H05K1/18 ,  G06F17/50

CPC分类号： H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

摘要： A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.