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    Reading circuit and method for a non-volatile memory device
    21.
    发明授权
    Reading circuit and method for a non-volatile memory device 有权

    公开(公告)号：US10593410B2

    公开(公告)日：2020-03-17

    申请号：US16145734

    申请日：2018-09-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Carmelo Paolino ,  Antonino Conte ,  Anna Rita Maria Lipani

    IPC: G11C16/06 ,  G11C16/28 ,  G11C16/04 ,  G11C16/24 ,  G11C7/06 ,  G11C7/08 ,  G11C13/00

    Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.

    Phase-change memory with selectors in BJT technology and differential-reading method thereof
    22.
    发明授权
    Phase-change memory with selectors in BJT technology and differential-reading method thereof 有权

    公开(公告)号：US10573382B2

    公开(公告)日：2020-02-25

    申请号：US16133097

    申请日：2018-09-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C7/12 ,  G11C5/14 ,  H01L45/00

    Abstract: A phase-change memory device includes a memory array including a first memory cell and a second memory cell, each comprising a phase-change element and a selector, connected respectively to a first local bitline and a second local bitline, which are in turn connected, respectively, to a first main bitline and a second main bitline. The parasitic capacitance of the main bitlines is precharged at a supply voltage. When the local bitlines are selected to access a respective logic datum stored in the phase-change element, the parasitic capacitance of the local bitlines is first charged using the charge previously stored in the parasitic capacitance of the main bitlines and then discharged through the respective phase-change elements. Reading of the logic datum is made by comparing the discharge times.

    Reading circuit with a shifting stage and corresponding reading method
    23.
    发明授权
    Reading circuit with a shifting stage and corresponding reading method 有权

    公开(公告)号：US10127966B2

    公开(公告)日：2018-11-13

    申请号：US15389751

    申请日：2016-12-23

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

    Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

    IPC: G11C11/24 ,  G04F10/10

    Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

    Dynamic sense amplifier with offset compensation
    25.
    发明授权
    Dynamic sense amplifier with offset compensation 有权

    公开(公告)号：US09698765B1

    公开(公告)日：2017-07-04

    申请号：US15049944

    申请日：2016-02-22

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

    Inventor： Francesco La Rosa ,  Antonino Conte

    IPC: G11C11/22 ,  G11C11/00 ,  H03K5/003 ,  H03K17/687 ,  G11C7/06 ,  G11C7/12

    CPC classification number: H03K5/003 ,  G11C7/06 ,  G11C7/065 ,  G11C7/12

    Abstract: A device includes a first and second inverters each having a signal input, signal output, high voltage supply terminal, and low voltage supply terminal. The signal input of the first inverter is coupled to the signal output of the second inverter, and the signal input of the second inverter is coupled to the signal output of the first inverter. A first transistor has a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to the high voltage supply terminal of the first inverter, and a control terminal coupled to a first node. A second transistor has a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to the high voltage supply terminal of the second inverter, and a control terminal coupled to a second node. First and second bit lines are capacitively coupled to the first and second nodes.

    Amplifier circuit with static consumption control and corresponding control method
    28.
    发明授权
    Amplifier circuit with static consumption control and corresponding control method 有权
    放大器电路具有静态消耗控制和相应的控制方式

    公开(公告)号：US09484872B1

    公开(公告)日：2016-11-01

    申请号：US14969042

    申请日：2015-12-15

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Antonino Conte ,  Alberto Jose' Di Martino

    IPC: H03F3/45 ,  H03M1/66 ,  G11C16/12 ,  G11C5/14

    CPC classification number: H03F3/45179 ,  G11C5/145 ,  G11C16/12 ,  H03F3/3027 ,  H03F3/45659 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2203/45116 ,  H03F2203/45424 ,  H03F2203/45431 ,  H03M1/66

    Abstract: An amplifier circuit may include an input amplification stage comprising a first amplifier having first and second differential inputs and a first output, and a second amplifier having first and second differential inputs and a second output. The amplifier circuit also includes an output amplification stage having first and second inputs respectively coupled to the first and second outputs of the input amplification stage, and an output configured to supply an output voltage based upon the input voltage by an amplification factor. The amplifier circuit comprises a feedback stage with a common-mode control stage configured to implement a comparison between the first differential voltage and the second differential voltage, and a reference voltage, and generate respective regulation currents on the first and second inputs of the output amplification stage to compensate for a common-mode variation of the first differential voltage and the second differential voltage.

    Abstract translation: 放大器电路可以包括输入放大级，其包括具有第一和第二差分输入和第一输出的第一放大器，以及具有第一和第二差分输入和第二输出的第二放大器。 放大器电路还包括输出放大级，其具有分别耦合到输入放大级的第一和第二输出的第一和第二输入以及被配置为基于输入电压提供放大因子的输出电压的输出。 放大器电路包括具有共模控制级的反馈级，配置为实现第一差分电压和第二差分电压之间的比较以及参考电压，并且在输出放大的第一和第二输入上产生相应的调节电流 以补偿第一差分电压和第二差分电压的共模变化。

    Error correction in memory devices by multiple readings with different references
    29.
    发明授权
    Error correction in memory devices by multiple readings with different references 有权
    通过不同参考的多个读数对存储器件进行错误校正

    公开(公告)号：US09430328B2

    公开(公告)日：2016-08-30

    申请号：US14597845

    申请日：2015-01-15

    Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

    Inventor： Antonino Conte ,  Kailash Khairnar

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F11/08 ,  G11C13/00

    CPC classification number: G06F11/1068 ,  G06F11/08 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/52 ,  G11C2013/0054

    Abstract: A memory device may include memory cells. The method may include receiving a request of reading a selected data word associated with a selected code word stored with an error correction code, and reading a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference. The method may include verifying the first code word, setting the selected code word according to the first code word in response to a positive verification, reading at least one second code word representing a second version of the selected code word, verifying the second code word, and setting the selected code word according to the second code word in response to a negative verification of the first code word and to a positive verification of the second code word.

    Abstract translation: 存储器件可以包括存储器单元。 该方法可以包括：接收读取与通过纠错码存储的所选码字相关联的所选择的数据字的请求，以及通过比较所选择的存储单元的状态来读取表示所选码字的第一版本的第一码字 第一个参考。 该方法可以包括验证第一代码字，响应于正验证，根据第一代码字设置所选择的代码字，读取表示所选代码字的第二版本的至少一个第二代码字，验证第二代码字 并且响应于第一代码字的否定验证和第二代码字的肯定验证，根据第二代码字设置所选择的代码字。

    Decoding architecture and method for phase change non-volatile memory devices
    30.
    发明授权
    Decoding architecture and method for phase change non-volatile memory devices 有权
    相变非易失性存储器件的解码架构和方法

    公开(公告)号：US08982615B2

    公开(公告)日：2015-03-17

    申请号：US13780280

    申请日：2013-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Francesca Grande ,  AlbertoJose′ Dimartino ,  Alfredo Signorello

    IPC: G11C11/00 ,  G11C8/00 ,  G11C13/00 ,  G11C8/12 ,  G11C7/12 ,  G11C8/10 ,  G11C5/14

    CPC classification number: G11C13/0009 ,  G11C5/146 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2207/005

    Abstract: A decoding system for a phase change non-volatile memory device having a memory array may include a column decoder that selects at least one column of the memory array during programming operations. The decoding system includes a selection circuit that includes selection switches on a number of hierarchical decoding levels for defining a conductive path between at least one column and a driving stage. A biasing circuit may supply biasing signals to the selection switches for defining the first conductive path and bringing the selected column to a programming voltage value. The programming selection circuit may have protection elements between columns and the selection switches. The selection switches and the protection elements may include metal oxide semiconductor (MOS) transistors having an upper threshold voltage level lower than the programming voltage.

    Abstract translation: 具有存储器阵列的相变非易失性存储器件的解码系统可以包括在编程操作期间选择存储器阵列的至少一列的列解码器。 解码系统包括选择电路，其包括用于限定至少一个列和驱动级之间的导电路径的多个分层解码级别的选择开关。 偏置电路可以向选择开关提供偏置信号，用于限定第一导电路径并使所选列进入编程电压值。 编程选择电路可以具有列和选择开关之间的保护元件。 选择开关和保护元件可以包括具有比编程电压低的上阈值电压电平的金属氧化物半导体（MOS）晶体管。

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