公开(公告)号：US08836142B2

公开(公告)日：2014-09-16

申请号：US13911569

申请日：2013-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeun-Sang Park ,  Byung-Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Kwangjin Moon ,  Sukchul Bang

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.

Abstract translation: 公开了半导体器件。 半导体器件可以包括具有彼此相对的第一表面和第二表面的半导体衬底和形成在第二表面的一部分处的衬垫沟槽，穿透半导体衬底并从衬底的底表面突出的通孔 沟。 掩埋焊盘可以设置在焊盘沟槽中并且可以围绕通孔。

公开(公告)号：US09865581B2

公开(公告)日：2018-01-09

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

公开(公告)号：US20170062308A1

公开(公告)日：2017-03-02

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-ll Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

Abstract translation: 一种半导体器件包括穿透衬底的通孔结构，所述通孔结构的一部分在所述衬底的表面上暴露，所述保护层图案结构设置在所述衬底的表面上并且包括第一保护层图案和第二保护 所述第一保护层图案围绕所述通孔结构的所述暴露部分的下侧壁并暴露所述通孔结构的所述暴露部分的上侧壁，所述第二保护层图案暴露所述第一保护的顶表面的一部分 所述衬垫结构设置在所述通孔结构和所述保护层图案结构上并且覆盖由所述第二保护层图案暴露的所述第一保护层图案的顶表面。

公开(公告)号：US09496218B2

公开(公告)日：2016-11-15

申请号：US13919580

申请日：2013-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Sun Lee ,  Kun-Sang Park ,  Byung-Lyul Park ,  Seong-min Son ,  Gil-heyun Choi

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L21/288 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/2885 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.

Abstract translation: 提供了一种包括贯穿硅通孔（TSV）结构的集成电路器件及其制造方法。 集成电路器件可以包括穿透半导体结构的TSV结构。 TSV结构可以包括包括第一浓度的杂质的第一通过电极单元和包括大于第一浓度的第二浓度的杂质的第二通过电极单元。

公开(公告)号：US09431341B2

公开(公告)日：2016-08-30

申请号：US14329749

申请日：2014-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Byung-Lyul Park ,  Ji-Soon Park ,  Si-Young Choi

IPC: H01L29/40 ,  H01L23/528 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08146 ,  H01L2224/80894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.

Abstract translation: 提供一种半导体器件。 半导体器件包括在衬底的第一表面上限定金属图案的钝化层，设置在衬底的第二表面上的层间绝缘层，以及形成在金属图案和第一钝化层之间的压电图案 基板的表面。 通过硅通孔和/或焊盘可以仅通过施加压力而不进行热处理直接结合到另一个通硅通孔和/或另一焊盘。

公开(公告)号：US09236349B2

公开(公告)日：2016-01-12

申请号：US13943828

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Ho-Jin Lee ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC: H01L23/538 ,  H01L23/485 ,  H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/6836 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract translation: 提供了包括通孔结构和再分配结构的半导体器件。 半导体器件可以包括在衬底的第一侧上的内部电路，垂直穿过衬底以与内部电路中的一个电连接的通孔结构，在衬底的第二侧上的再分配结构，并且电连接到通孔 通孔结构，以及在基板的第二面和再分布结构之间的绝缘层。 再分布结构可以包括再分配阻挡层和再分布金属层，再分布阻挡层可以在再分布金属层的底表面上延伸并且可以部分地围绕再分布金属层的一侧。

公开(公告)号：US09076849B2

公开(公告)日：2015-07-07

申请号：US14094963

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Ho An ,  Byung-Lyul Park ,  Soyoung Lee ,  Gilheyun Choi

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening.

Abstract translation: 半导体器件以及制造半导体器件的方法包括：通过基板的第一表面形成通孔，所述通孔与面向第一表面的第二表面间隔开，在通孔中形成第一导电图案，形成 在所述基板的第一表面上的绝缘垫层，所述绝缘垫具有暴露所述第一导电图案的开口，对所述第一导电图案进行热处理，以形成从所述第一导电图案的顶表面朝向所述开口突出的突起 ，然后在开口中形成第二导电图案。

公开(公告)号：US20140008815A1

公开(公告)日：2014-01-09

申请号：US13911569

申请日：2013-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeun-Sang Park ,  Byung-Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Kwangjin Moon ,  Sukchul Bang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.

Abstract translation: 公开了半导体器件。 半导体器件可以包括具有彼此相对的第一表面和第二表面的半导体衬底和形成在第二表面的一部分处的衬垫沟槽，穿透半导体衬底并从衬底的底表面突出的通孔 沟。 掩埋焊盘可以设置在焊盘沟槽中并且可以围绕通孔。

公开(公告)号：US20130313722A1

公开(公告)日：2013-11-28

申请号：US13763294

申请日：2013-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Son-Kwan Hwang ,  Byung-Lyul Park ,  Hyun-Soo Chung ,  Jin-Ho Chun ,  Gil-Heyun Choi

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K2201/09563 ,  H01L2924/00

Abstract: A semiconductor device includes an insulating layer on a surface of a substrate, a through-via structure vertically passing through the substrate and the insulating layer and being exposed on the insulating layer, and a via pad on a surface of the exposed through-via structure. The via pad includes a via pad body, and a via pad inlay below the via pad body and protruding into the insulating layer and surrounding the through-via structure. The via pad body and the via pad inlay include a via pad barrier layer directly on the insulating layer and a via pad metal layer on the via pad barrier layer.

Abstract translation: 半导体器件包括在衬底的表面上的绝缘层，垂直穿过衬底和绝缘层并且暴露在绝缘层上的通孔结构，以及暴露的通孔结构的表面上的通孔焊盘 。 通孔焊盘包括通孔焊盘主体和通孔焊盘嵌入到通孔焊盘主体下方并突出到绝缘层中并且围绕通孔结构。 通孔焊盘主体和通孔焊盘嵌体包括直接在绝缘层上的通孔焊盘阻挡层和通孔焊盘阻挡层上的通孔焊盘金属层。