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公开(公告)号：US11874513B2
公开(公告)日：2024-01-16
申请号：US18162712
申请日：2023-02-01
发明人： Chia-Lun Chang , Ching-Hua Hsieh , Cheng-Ting Chen , Hsiu-Jen Lin , Hsuan-Ting Kuo , Chia-Shen Cheng , Chih-Chiang Tsao
IPC分类号： G02B6/42 , H01L23/538 , H01L25/18 , H01L23/31 , H01L23/00 , H01L25/00 , H01L21/683 , H01L21/56 , G02B6/43 , H05K1/18 , H05K1/02
CPC分类号： G02B6/428 , G02B6/4214 , G02B6/4253 , G02B6/43 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/3128 , H01L23/5386 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/18 , H01L25/50 , H05K1/0274 , H05K1/181 , H01L21/568 , H01L2221/68359 , H01L2221/68372 , H01L2221/68381 , H01L2224/215 , H01L2224/24225 , H01L2224/821 , H01L2224/82005 , H01L2224/95001 , H01L2924/12042 , H01L2924/12043 , H05K2201/10121 , H05K2201/10151 , H05K2201/2054
摘要： In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.
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公开(公告)号：US20230168451A1
公开(公告)日：2023-06-01
申请号：US18162712
申请日：2023-02-01
发明人： Chia-Lun Chang , Ching-Hua Hsieh , Cheng-Ting Chen , Hsiu-Jen Lin , Hsuan-Ting Kuo , Chia-Shen Cheng , Chih-Chiang Tsao
IPC分类号： G02B6/42 , H01L23/538 , H01L25/18 , H01L23/31 , H01L23/00 , H01L25/00 , H01L21/683 , H01L21/56 , G02B6/43 , H05K1/18 , H05K1/02
CPC分类号： G02B6/428 , H01L23/5386 , G02B6/4214 , H01L25/18 , H01L23/3128 , H01L24/24 , H01L25/50 , H01L24/82 , H01L21/6835 , H01L21/561 , H01L24/96 , G02B6/4253 , H01L21/565 , G02B6/43 , H05K1/181 , H05K1/0274 , H05K2201/2054 , H05K2201/10121 , H01L2224/95001 , H01L21/568 , H01L2224/821 , H05K2201/10151 , H01L2224/82005 , H01L2221/68359 , H01L2221/68372 , H01L2221/68381 , H01L2224/215 , H01L2224/24225 , H01L2924/12042 , H01L2924/12043
摘要： In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.
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公开(公告)号：US11158605B2
公开(公告)日：2021-10-26
申请号：US15791071
申请日：2017-10-23
发明人： Chun-Cheng Lin , Chung-Shi Liu , Kuei-Wei Huang , Cheng-Ting Chen , Wei-Hung Lin , Ming-Da Cheng
IPC分类号： H01L25/065 , H01L23/498 , H01L25/10 , H01L21/48 , H01L21/56 , H01L23/00 , H01L25/00 , H01L21/027 , H01L21/768 , H01L23/31
摘要： A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
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公开(公告)号：US10512124B2
公开(公告)日：2019-12-17
申请号：US15380671
申请日：2016-12-15
发明人： Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
IPC分类号： B23K31/02 , H01L21/00 , H01L23/00 , H05B3/02 , H01L21/677 , H01L21/683 , B23K3/08 , B23K101/40
摘要： A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
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公开(公告)号：US10504815B2
公开(公告)日：2019-12-10
申请号：US15940623
申请日：2018-03-29
发明人： Hao-Jan Pei , Wei-Yu Chen , Chia-Shen Cheng , Chih-Chiang Tsao , Cheng-Ting Chen , Chia-Lun Chang , Chih-Wei Lin , Hsiu-Jen Lin , Ching-Hua Hsieh , Chung-Shi Liu
IPC分类号： H01L23/373 , H01L23/50 , H01L23/00 , H01L21/56 , H01L21/48 , H01L23/31 , H01L23/367 , H01L23/538 , H01L25/10 , H01L23/498
摘要： A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
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公开(公告)号：US09799631B2
公开(公告)日：2017-10-24
申请号：US15443679
申请日：2017-02-27
发明人： Chun-Cheng Lin , Chung-Shi Liu , Kuei-Wei Huang , Cheng-Ting Chen , Wei-Hung Lin , Ming-Da Cheng
IPC分类号： H01L23/48 , H01L25/065 , H01L23/00 , H01L25/00 , H01L21/768 , H01L21/027 , H01L21/56 , H01L23/498 , H01L21/48 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/0273 , H01L21/486 , H01L21/56 , H01L21/76898 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2224/0231 , H01L2224/0239 , H01L2224/03452 , H01L2224/0401 , H01L2224/05083 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/1131 , H01L2224/11424 , H01L2224/1152 , H01L2224/1162 , H01L2224/11825 , H01L2224/11849 , H01L2224/13024 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13611 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16238 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01048 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/12042 , H01L2924/15311 , H01L2924/15321 , H01L2924/15747 , H01L2924/18161 , H01L2924/2064 , H01L2924/20641 , H01L2924/20642 , H01L2924/00014 , H01L2924/00
摘要： A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
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公开(公告)号：US09627234B2
公开(公告)日：2017-04-18
申请号：US14208124
申请日：2014-03-13
发明人： Hui-Min Huang , Chih-Wei Lin , Cheng-Ting Chen , Ming-Da Cheng , Chung-Shi Liu
CPC分类号： H01L21/6708 , G03F7/42 , H01L21/02052 , H01L21/02057
摘要： A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path.
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公开(公告)号：US09437564B2
公开(公告)日：2016-09-06
申请号：US13937599
申请日：2013-07-09
发明人： Wen-Hsiung Lu , Hsuan-Ting Kuo , Cheng-Ting Chen , Ai-Tee Ang , Ming-Da Cheng , Chung-Shi Liu
CPC分类号： H01L24/13 , H01L21/566 , H01L23/3171 , H01L23/3192 , H01L24/05 , H01L24/11 , H01L2224/02331 , H01L2224/0401 , H01L2224/05008 , H01L2224/05547 , H01L2224/05548 , H01L2224/05571 , H01L2224/05572 , H01L2224/10126 , H01L2224/1191 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13561 , H01L2224/13582 , H01L2224/13611 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2924/12042 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/014 , H01L2924/01029 , H01L2924/01047 , H01L2924/00012 , H01L2924/00014
摘要： A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer.
摘要翻译： 一种结构包括形成在半导体衬底上的钝化层，由钝化层包围的连接焊盘，形成在钝化层上的再分配层，其中再分配层连接到连接焊盘，形成在再分配层上的凸块，其中 凸块连接到再分布层和在再分布层上形成的模塑料层。 模塑料层包括平坦部分，其中凸起的底部嵌入在模塑料层的平坦部分和突出部分中，其中凸起的中间部分被模塑料层的突出部分包围 。
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公开(公告)号：US20160148889A1
公开(公告)日：2016-05-26
申请号：US15011030
申请日：2016-01-29
发明人： Cheng-Ting Chen , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu , Mirng-Ji Lii
IPC分类号： H01L23/00 , H01L23/498 , H01L25/065 , H01L23/31
CPC分类号： H01L24/16 , H01L23/3114 , H01L23/3142 , H01L23/3157 , H01L23/49816 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L2224/0345 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05681 , H01L2224/05684 , H01L2224/08238 , H01L2224/11334 , H01L2224/1181 , H01L2224/11849 , H01L2224/119 , H01L2224/1191 , H01L2224/13005 , H01L2224/13007 , H01L2224/13016 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13184 , H01L2224/1329 , H01L2224/133 , H01L2224/1601 , H01L2224/16052 , H01L2224/16112 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81024 , H01L2224/81191 , H01L2224/81815 , H01L2225/06513 , H01L2924/181 , H01L2924/18161 , H01L2924/20641 , H01L2924/20642 , H01R43/0235 , H01L2924/207 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/00
摘要： Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.
摘要翻译： 这里提出了一种用于形成它的互连和方法，所述方法包括在设置在第一基板的第一表面上的安装焊盘的安装表面上形成互连，所述互连包括导电材料，可选地焊料或金属，所述互连 避免安装垫的侧面。 将模塑料施加到第一基板的第一表面并且在互连件周围模制以覆盖互连件的至少下部，并且第二基板可以安装在互连件上。 互连可以包括设置在第一和第二基板之间的互连材料和设置在第一基板的表面上的模制化合物，以及暴露互连的一部分。 互连材料的侧壁以与垂直于第一衬底的平面成小于约30度的角度接触安装衬垫。
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公开(公告)号：US20140131861A1
公开(公告)日：2014-05-15
申请号：US14096435
申请日：2013-12-04
发明人： Chen-Fa Lu , Chung-Shi Liu , Chen-Hua Yu , Wei-Yu Chen , Cheng-Ting Chen
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L23/293 , H01L23/3171 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0362 , H01L2224/03831 , H01L2224/03901 , H01L2224/0401 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/1147 , H01L2224/11622 , H01L2224/1181 , H01L2224/1183 , H01L2224/11849 , H01L2224/11901 , H01L2224/13111 , H01L2224/13116 , H01L2224/93 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/12044 , H01L2924/14 , H01L2924/1434 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H05K3/28 , H05K3/3478 , H05K3/4007 , H01L2224/11 , H01L2224/05552 , H01L2924/00 , H01L2924/1082
摘要： A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.
摘要翻译： 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。
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