公开(公告)号：US20180274088A1

公开(公告)日：2018-09-27

申请号：US15763782

申请日：2016-09-09

申请人： MIE UNIVERSITY

发明人： Hideto MIYAKE

IPC分类号： C23C16/18 ,  C23C16/34 ,  C30B29/38 ,  C30B29/40 ,  H01L21/205 ,  H01L21/02 ,  H01L21/324

CPC分类号： C23C16/18 ,  C23C16/34 ,  C30B29/38 ,  C30B29/406 ,  H01L21/02172 ,  H01L21/02205 ,  H01L21/02304 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/3245

摘要： A method for manufacturing a nitride semiconductor substrate includes: a preparation step of preparing a sapphire substrate; and a buffer layer forming step of forming an AlN buffer layer on the sapphire substrate, wherein the buffer layer forming step includes: a group III nitride semiconductor forming step of forming a precursor of an AlN buffer layer on the sapphire substrate; and an annealing step of annealing the sapphire substrate on which the precursor of the AlN buffer layer is formed in a gas-tight state in which a principal surface of the precursor of the AlN buffer layer is covered with a cover member (such as a sapphire substrate) for inhibiting a component of the group III nitride semiconductor from dissociating from the principal surface of the formed precursor of the AlN buffer layer.

公开(公告)号：US10083831B2

公开(公告)日：2018-09-25

申请号：US15454327

申请日：2017-03-09

申请人： Sumitomo Electric Industries, Ltd.

发明人： Masaya Okada ,  Fuminori Mitsuhashi ,  Yasunori Tateno ,  Masaki Ueno

IPC分类号： H01L21/02 ,  H01L29/786 ,  H01L29/16 ,  H01L29/04

CPC分类号： H01L21/02527 ,  H01L21/02376 ,  H01L21/02389 ,  H01L21/02417 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02516 ,  H01L21/02609 ,  H01L21/02612 ,  H01L29/045 ,  H01L29/1606 ,  H01L29/267 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78684

摘要： A substrate includes: a support substrate having a first main surface and a surface layer region which includes at least the first main surface and is formed of any one material selected from the group consisting of boron nitride, molybdenum disulfide, tungsten disulfide, niobium disulfide, and aluminum nitride; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of the material forming the surface layer region. Accordingly, the substrate is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.

公开(公告)号：US10078059B2

公开(公告)日：2018-09-18

申请号：US15398451

申请日：2017-01-04

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Keiji Ishibashi ,  Tokiko Kaji ,  Seiji Nakahata ,  Takayuki Nishiura

IPC分类号： C30B25/02 ,  G01N23/207 ,  H01L29/04 ,  H01L29/20 ,  H01L21/02 ,  H01L21/66 ,  G01B15/08 ,  C30B25/20 ,  C30B25/18 ,  C30B29/40 ,  C30B33/10

CPC分类号： G01N23/207 ,  C30B25/186 ,  C30B25/20 ,  C30B29/38 ,  C30B29/403 ,  C30B29/406 ,  C30B33/00 ,  C30B33/10 ,  G01B15/08 ,  G01N2223/602 ,  G01N2223/634 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/0254 ,  H01L22/12 ,  H01L29/04 ,  H01L29/045 ,  H01L29/2003 ,  Y10T428/2978

摘要： A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1−d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 μm and the plane spacing d2 at the X-ray penetration depth of 5 μm is equal to or lower than 2.1×10−3. The above configuration provides the nitride crystal having a crystal surface layer that is evaluated directly and reliably without breaking the crystal so that it can be used in a preferred fashion as a substrate for a semiconductor device as well as the nitride crystal substrate, an epilayer-containing nitride crystal substrate, a semiconductor device and a method of manufacturing the same.

公开(公告)号：US20180258551A1

公开(公告)日：2018-09-13

申请号：US15761197

申请日：2016-08-31

申请人： FORSCHUNGSVERBUND BERLIN E.V.

发明人： Andrea Dittmar ,  Carsten Hartmann ,  Jürgen Wollweber ,  Matthias Bickermann

IPC分类号： C30B29/40 ,  C30B23/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L33/32 ,  H01L33/00 ,  H01L33/06 ,  H01L29/15

CPC分类号： C30B29/403 ,  C30B23/005 ,  C30B23/066 ,  H01L21/02389 ,  H01L21/0254 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L33/0025 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/32 ,  H01S5/0206 ,  H01S5/343

摘要： The invention concerns a method for the production of single crystal aluminium nitride doped with scandium and/or yttrium, with scandium and/or yttrium contents in the range 0.01 atom % to 50 atom % with respect to 100 atom % of the total quantity of the doped aluminium nitride, characterized in that in a crucible, in the presence of a gas selected from nitrogen or a noble gas, or a mixture of nitrogen and a noble gas: a doping material selected from scandium, yttrium, scandium nitride or yttrium nitride or a mixture thereof and a source material formed from aluminium nitride are sublimated and recondensed onto a seed material which is selected from aluminium nitride or aluminium nitride doped with scandium and/or yttrium. The invention also concerns a corresponding device as well as the corresponding single crystal products and their use, whereupon the basis for novel components based on layers or stacks of layers of aluminium gallium nitride, indium aluminium nitride or indium aluminium gallium nitride is generated.

公开(公告)号：US20180247810A1

公开(公告)日：2018-08-30

申请号：US15965065

申请日：2018-04-27

申请人： NGK INSULATORS, LTD.

发明人： Mikiya ICHIMURA ,  Sota MAEHARA ,  Yoshitaka KURAOKA

IPC分类号： H01L21/02 ,  C23C16/34 ,  C30B29/40 ,  C30B19/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

CPC分类号： H01L21/02389 ,  C23C16/303 ,  C23C16/34 ,  C30B19/02 ,  C30B29/406 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/205 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/66007 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/812

摘要： Provided is an epitaxial substrate for semiconductor elements which suppresses an occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN being doped with Zn; a buffer layer being adjacent to the free-standing substrate; a channel layer being adjacent to the buffer layer; and a barrier layer being provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer formed of Al-doped GaN and suppresses diffusion of Zn from the free-standing substrate into the channel layer.

公开(公告)号：US20180182915A1

公开(公告)日：2018-06-28

申请号：US15846379

申请日：2017-12-19

申请人： TOYODA GOSEI CO., LTD.

发明人： Yoshiki Saito ,  Daisuke Shinoda

IPC分类号： H01L33/00

CPC分类号： H01L33/0075 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/02389 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658 ,  H01L33/32

摘要： To provide a method for producing a Group III nitride semiconductor light-emitting device using a substrate containing Al such as AlN substrate while suppressing polarity inversion. The production method comprising an oxide film formation step, a first Group III nitride layer formation step, a first semiconductor layer formation step, a light-emitting layer formation step, and a second semiconductor layer formation step. In the production method, an AlN substrate or AlGaN substrate is employed. In the oxide film formation step, an oxide film containing Al atoms, N atoms, and O atoms is formed. In the first Group III nitride layer formation step, an AlN layer or AlGaN layer is formed as the first Group III nitride layer under the condition that the substrate temperature 1200° C. to 1450° C.

公开(公告)号：US20180182881A1

公开(公告)日：2018-06-28

申请号：US15796705

申请日：2017-10-27

申请人： SixPoint Materials, Inc.

发明人： Tadao Hashimoto ,  Daisuke Ueda

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/32 ,  H01L29/36 ,  H01L29/45 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L29/66 ,  C30B29/40 ,  C30B7/10 ,  C30B25/20

CPC分类号： H01L29/7371 ,  C30B7/105 ,  C30B25/20 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/02639 ,  H01L21/28575 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/36 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/66204 ,  H01L29/66219 ,  H01L29/66318 ,  H01L29/66356 ,  H01L29/66462 ,  H01L29/66924 ,  H01L29/7391 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/8083 ,  H01L29/8611

摘要： The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

公开(公告)号：US20180182620A1

公开(公告)日：2018-06-28

申请号：US15847716

申请日：2017-12-19

申请人： QROMIS, Inc.

发明人： Vladimir Odnoblyudov ,  Dilip Risbud ,  Ozgur Aktas

IPC分类号： H01L21/02 ,  H01L21/683 ,  H01L29/66 ,  H01L21/78

CPC分类号： H01L21/02505 ,  H01L21/02002 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/6831 ,  H01L21/7806 ,  H01L29/66212 ,  H01L29/66522 ,  H01L29/66712

摘要： A method of forming a semiconductor device includes providing an engineered substrate. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer. The method further includes forming a Schottky diode coupled to the engineered substrate. The Schottky diode has a top surface and a bottom surface. the bottom surface is coupled to the substantially single crystalline silicon layer. The method further includes forming a Schottky contact coupled to the top surface of the Schottky diode, forming a metal plating coupled to the Schottky contact, removing the engineered substrate to expose the bottom surface of the Schottky diode, and forming an ohmic contact on the bottom surface of the Schottky diode.

公开(公告)号：US09947530B2

公开(公告)日：2018-04-17

申请号：US15399898

申请日：2017-01-06

申请人： Samsung Electronics Co., Ltd.

发明人： Young Jo Tak ,  Sam Mook Kang ,  Mi Hyun Kim ,  Jun Youn Kim ,  Young Soo Park

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L21/0254 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/304 ,  H01L21/30604

摘要： A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.

公开(公告)号：US09941168B1

公开(公告)日：2018-04-10

申请号：US15631309

申请日：2017-06-23

申请人： KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

发明人： Sanghyeon Kim ,  Hyung-jun Kim ,  Jae-Phil Shim ,  Seong Kwang Kim ,  Won Jun Choi

IPC分类号： H01L21/78 ,  H01L21/306 ,  H01L21/02

CPC分类号： H01L21/7813 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/30617

摘要： A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.