公开(公告)号：US06444919B1

公开(公告)日：2002-09-03

申请号：US08477054

申请日：1995-06-07

申请人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

发明人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

IPC分类号： H05K103

CPC分类号： H01L23/5382 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0286 ,  H05K1/0289 ,  H05K3/467 ,  H01L2924/00

摘要： A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

摘要翻译： 基板上的薄膜布线方案。 薄膜布线方案包括在基板上的第一和第二芯片位置的每一个处的多个芯片连接焊盘，散布在第一和第二芯片位置中的每一个的芯片连接焊盘之间的多个定向布线，至少一个 所述定向布线与所述第一和第二芯片位置中的每一个处的所述其它方向布线中的至少一个正交;以及多个芯片布线，其将所述第一芯片位置处的方向布线与所述定向布线连接， 第二个芯片站点。

公开(公告)号：US06434017B1

公开(公告)日：2002-08-13

申请号：US09235760

申请日：1999-01-25

申请人： Kaoru Iwabuchi

发明人： Kaoru Iwabuchi

IPC分类号： H05K103

CPC分类号： H01L21/563 ,  H01L23/145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01087 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device in a chip size package form having a high durability and reliability and realizing a small size with high density, and an electronic apparatus mounting the same, connected to a motherboard by soldering, comprising a semiconductor chip wherein bumps are formed on pad portions thereof; an interposer supporting the bumps mechanically and having through-holes wherein conductors are formed and connected to the bumps electrically; and a sealing resin buried between the semiconductor chip and the interposer, wherein the interposer is formed from a material having a higher glass transition temperature than a curing temperature of the sealing resin, a coefficient of linear expansion of the interposer is of a value substantially intermediate between that of the motherboard and that of the semiconductor chip, and/or the interposer is formed from a material having a bending strength of 400 MPa or more.

摘要翻译： 一种芯片尺寸封装形式的半导体器件，其具有高耐久性和可靠性，并且实现了具有高密度的小尺寸和安装该半导体器件的电子设备，其通过焊接连接到母板，包括半导体芯片，其中凸块形成在焊盘部分上 的; 插入件，其机械地支撑所述凸块，并具有形成导体并且与所述凸块电连接的通孔; 以及埋在半导体芯片和插入件之间的密封树脂，其中所述插入件由具有比所述密封树脂的固化温度更高的玻璃化转变温度的材料形成，所述插入件的线性膨胀系数具有基本上中间的值 在主板和半导体芯片的主板之间，和/或插入件由弯曲强度为400MPa以上的材料形成。

公开(公告)号：US06433284B1

公开(公告)日：2002-08-13

申请号：US09749030

申请日：2000-12-26

申请人： Gwun-Jin Lin ,  Chi-Kuang Hwang ,  Ching-Cheng Tien

发明人： Gwun-Jin Lin ,  Chi-Kuang Hwang ,  Ching-Cheng Tien

IPC分类号： H05K103

CPC分类号： H05K1/028 ,  H05K1/024 ,  H05K2201/09063 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09727

摘要： A partially cut multi-planar flexible printed circuit comprises a substrate, a set of signal conducting elements for differential mode and common mode, a power supply and/or ground. The multi-planar flexible printed circuit is formed by partially grouped cutting a flexible printed circuit at a proper position so that the cross-sectional area of the multi-planar flexible printed circuit at the cut portion can fit in with a small round or square splice hole in addition to a flat rectangular slit for connecting, for example, a liquid crystal display with a notebook computer. Moreover, intervals between edges of a substrate and a plurality of transmission lines are preferably greater than three times of thickness of the substrate.

摘要翻译： 部分切割的多平面柔性印刷电路包括基板，用于差模和共模的一组信号传导元件，电源和/或接地。 多平面柔性印刷电路通过将柔性印刷电路部分地分组切割成适当的位置而形成，使得在切割部分处的多平面柔性印刷电路的横截面积可以用小的圆形或方形接头 除了用于连接例如具有笔记本计算机的液晶显示器的扁平矩形狭缝之外。 此外，衬底的边缘和多条传输线之间的间隔优选大于衬底厚度的三倍。

公开(公告)号：US06410858B1

公开(公告)日：2002-06-25

申请号：US09736886

申请日：2000-12-14

申请人： Masayuki Sasaki ,  Kazunari Imai

发明人： Masayuki Sasaki ,  Kazunari Imai

IPC分类号： H05K103

CPC分类号： H05K3/4641 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H05K2203/0152 ,  Y10T29/435 ,  H01L2224/05599

摘要： A multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer, in which said wiring board further has, incorporated therein, at least one capacitor element which comprises a sandwiched structure of a lower electrode-forming metallic layer having formed thereon at least one recess portion, a dielectric layer formed over the lower electrode-forming metallic layer, and an upper electrode-forming metallic layer formed over the dielectric layer, and its production process. The semiconductor device comprising the multilayered wiring board having mounted thereon a semiconductor element is also disclosed.

摘要翻译： 一种多层布线基板，包括至少两个布线层和层间绝缘层，其中所述布线板还包括至少一个电容器元件，该电容器元件包括形成在其上的下电极形成金属层的夹层结构 至少一个凹部，形成在下电极形成金属层上的电介质层和形成在电介质层上的上电极形成金属层及其制造方法。 还公开了包括其上安装有半导体元件的多层布线板的半导体器件。

公开(公告)号：US06384340B1

公开(公告)日：2002-05-07

申请号：US09800408

申请日：2001-03-06

申请人： Yu-Chiang Cheng

发明人： Yu-Chiang Cheng

IPC分类号： H05K103

CPC分类号： H05K1/024 ,  H05K1/0298 ,  H05K3/4688 ,  H05K2201/0145 ,  H05K2201/0191 ,  H05K2201/09327

摘要： A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer, and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.2 mm. Each of the first and fifth insulating substrates has a thickness ranging from 4.175 to 4.725 mil. Each of the second and fourth insulating substrates has a thickness ranging from 5.7 to 6.3 mil. The third insulating substrate has a thickness ranging to 16.8 mil.

摘要翻译： 多层电路板包括第一，第二，第三，第四和第五绝缘基板，第一，第二，第三和第四信号布线层，接地布线层和电源布线层。 绝缘基板和布线层彼此压接，形成约1.2mm厚度的电路板。 第一和第五绝缘基板中的每一个的厚度范围为4.175至4.725密耳。 第二绝缘基板和第四绝缘基板中的每一个具有5.7至6.3密耳的厚度。 第三绝缘基板的厚度为16.8密耳。

公开(公告)号：US06329604B1

公开(公告)日：2001-12-11

申请号：US09635175

申请日：2000-08-09

申请人： Kenji Koya

发明人： Kenji Koya

IPC分类号： H05K103

CPC分类号： H05K1/0219 ,  H05K1/0289 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09718

摘要： A multilayer printed wiring board prevents unnecessary emission of electromagnetic waves. The board includes at least two signal wiring layers, at least one ground layer, at least one power source layer, and a ground plane. The board further includes ground wiring adjacent to signal wiring in a signal wiring layer farther apart from said ground layer, the ground wiring being in the signal wiring layer. The ground wiring serves as a return current path for a signal current flowing in the signal wiring. In this structure, the return current path is reserved adjacent to the signal current path and the signal wiring is lower in impedance than the ground plane. The current can be fed back through a shorter closed loop. It is therefore possible to form a small loop to pass a signal current returning to a ground point and flowing through each signal wiring arranged in the board and a return current of the signal current. This minimizes unnecessary emission of electromagnetic waves. It is also possible to form a small loop to pass a signal current returning to a ground point and flowing through each signal wiring in at least two different layers connected via a through-hole to each other and a return current of the signal current.

摘要翻译： 多层印刷线路板防止电磁波的不必要的发射。 该板包括至少两个信号布线层，至少一个接地层，至少一个电源层和接地层。 该板还包括与信号布线相邻的接地布线，该布线在远离所述接地层的信号布线层中，接地布线在信号布线层中。 接地线作为在信号布线中流动的信号电流的返回电流路径。 在这种结构中，返回电流路径被保留为与信号电流路径相邻，并且信号布线的阻抗比接地层低。 电流可通过较短的闭环反馈。 因此，可以形成一个小环路，以传递返回到接地点并流过布置在电路板中的每个信号布线的信号电流和信号电流的返回电流。 这使得电磁波的不必要的发射最小化。 还可以形成一个小环路，以将通过通孔连接的至少两个不同层中的每个信号布线的信号电流传递到接地点并流过信号电流的返回电流。

公开(公告)号：US06329065B1

公开(公告)日：2001-12-11

申请号：US09378849

申请日：1999-08-23

申请人： Masanobu Ishida ,  Shigeki Yamada ,  Yasuhiko Yoshihara ,  Masamitsu Onitani

发明人： Masanobu Ishida ,  Shigeki Yamada ,  Yasuhiko Yoshihara ,  Masamitsu Onitani

IPC分类号： H05K103

CPC分类号： H01L23/49838 ,  B32B18/00 ,  C04B35/117 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3213 ,  C04B2235/3267 ,  C04B2235/3418 ,  C04B2235/5436 ,  C04B2235/656 ,  C04B2235/6582 ,  C04B2235/768 ,  C04B2235/77 ,  C04B2235/9615 ,  C04B2235/963 ,  C04B2237/343 ,  C04B2237/62 ,  H01L23/15 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T428/2438 ,  Y10T428/24876 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

摘要： A wiring board having an insulating substrate of aluminum oxide ceramics and a surface wiring layer formed on the surface of said insulating substrate, wherein the aluminum oxide ceramics constituting said insulating substrate contains a manganese compound in an amount of from 2.0 to 10.0% by weight in terms of MnO2, and has a relative density of not smaller than 95%, and said surface wiring layer contains copper in an amount of from 10 to 70% by volume and at least one high-melting metal selected from the group consisting of tungsten and molybdenum in an amount of from 30 to 90% by volume, and further contains copper as a matrix, said copper matrix having a diffusion structure in which are diffused the particles of said high-melting metal having an average particle diameter of from 1 to 10 &mgr;m. The wiring board is prepared by co-firing the conducting paste for forming the surface wiring layer and the green sheet for forming the insulating substrate, and exhibits excellent heat conductivity and electric properties, and is particularly effectively used for the semiconductor devices that execute arithmetic operations at high speeds.

摘要翻译： 一种布线基板，其具有氧化铝陶瓷的绝缘基板和形成在所述绝缘基板的表面上的表面布线层，其中构成所述绝缘基板的氧化铝陶瓷含有2.0〜10.0重量％的锰化合物， MnO 2的比例相对密度不小于95％，所述表面布线层含有量为10〜70体积％的铜和选自钨和钨的至少一种高熔点金属 钼的量为30〜90体积％，进一步含有铜作为基体，所述铜基体具有扩散结构，其中所述扩散结构将平均粒径为1〜10的所述高熔点金属的粒子扩散 妈妈 通过共烧烧用于形成表面布线层的导电浆料和用于形成绝缘基板的生片来制备布线板，并且显示出优异的导热性和电性能，并且特别有效地用于执行算术运算的半导体器件 在高速下

公开(公告)号：US06307160B1

公开(公告)日：2001-10-23

申请号：US09182979

申请日：1998-10-29

申请人： Zequn Mei ,  Ali Eslambolchi

发明人： Zequn Mei ,  Ali Eslambolchi

IPC分类号： H05K103

CPC分类号： H01L24/10 ,  B23K35/26 ,  B23K35/262 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/3463 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2924/00014

摘要： A high-strength solder interconnect formed on a copper/electroless nickel/immersion gold metallization solder pad and method. The invention provides a low cost, high-strength solder interconnect on a copper/electroless nickel/immersion gold metallization (CENIGM) pad that can be formed at a temperature at or below the temperature used in eutectic tin-lead (Sn—Pb) solder applications. The invention includes a first substrate having a solder-wettable pad and a second substrate having a copper/electroless nickel/immersion gold metallization (CENIGM) solder pad. The invention also provides a solder interconnect between the solder-wettable pad and the CENIGM solder pad. The invention may provide a solder interconnect that includes a solder body including at least 2% indium (In) by weight and wetted to both the CENIGM solder pad and the solder-wettable pad. The invention may alternatively includes both a solder bump wetted to the solder-wettable pad and a solder joint, including at least 2% In by weight, wetted to the solder bump and the CENIGM solder pad. The method includes obtaining a first substrate including a solder-wettable pad and forming a solder bump on the solder-wettable pad. A second substrate is obtained including a CENIGM solder pad. Next, solder paste, including at least 5% In, is applied to the CENIGM solder pad and the solder bump is moved into contact with the solder paste. The solder paste is then reflowed to generate a solder joint wetted to the solder bump and the CENIGM solder pad.

摘要翻译： 在铜/无电镍/浸金金属化焊料焊盘上形成的高强度焊料互连和方法。 本发明在铜/无电镀镍/浸金金属化（CENIGM）焊盘上提供低成本，高强度的焊料互连，其可以在等于或低于共晶锡铅（Sn-Pb）焊料中使用的温度的温度下形成 应用程序。 本发明包括具有焊料可润湿焊盘的第一衬底和具有铜/无电镍/浸金金属化（CENIGM）焊盘的第二衬底。 本发明还提供了可焊接润湿垫和CENIGM焊盘之间的焊料互连。 本发明可以提供一种焊料互连，其包括焊料体，其包含至少2重量％的铟（In），并润湿CENIGM焊盘和可焊锡润湿垫。 本发明可以替代地包括润湿到可焊接可焊垫的焊料凸块和焊接接头，焊料接头包括至少2重量％的被润湿到焊料凸块和CENIGM焊盘的重量。 该方法包括获得包括可焊锡润湿垫的第一衬底，并在焊料润湿垫上形成焊料凸点。 获得包括CENIGM焊盘的第二基板。 接下来，将包括至少5％In的焊膏施加到CENIGM焊盘，并且使焊料凸块与焊膏接触。 然后将焊膏回流以产生润湿焊锡凸块和CENIGM焊盘的焊点。

公开(公告)号：US06284982B1

公开(公告)日：2001-09-04

申请号：US09641304

申请日：2000-08-18

申请人： Mark Kusner ,  Michael A. Centanni

发明人： Mark Kusner ,  Michael A. Centanni

IPC分类号： H05K103

CPC分类号： H05K1/167 ,  H05K1/095 ,  H05K3/025 ,  H05K3/388 ,  H05K3/4611 ,  H05K2201/0391 ,  H05K2203/061

摘要： A component for use in forming a multi-layer printed circuit comprised of a film substrate formed of a first polymeric material. At least one layer of a flash metal is applied to a first side of the film substrate, and at least one layer of copper is applied on the layer of flash metal. A discrete area of a resistive material is disposed on a second side of the film substrate.

摘要翻译： 一种用于形成由第一聚合物材料形成的薄膜基底构成的多层印刷电路的组件。 至少一层闪光金属被施加到薄膜基底的第一侧，并且至少一层铜被施加在闪光金属层上。 电阻材料的离散区域设置在膜基底的第二侧上。

公开(公告)号：US06833510B2

公开(公告)日：2004-12-21

申请号：US09971872

申请日：2001-10-04

申请人： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

发明人： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

IPC分类号： H05K103

CPC分类号： H01L22/20 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2224/85 ,  H01L2924/00

摘要： Semiconductor package support elements including cover members attached to one or more reject die sites are provided. Methods for making the support elements of the present invention and for making semiconductor packages using the same are also provided. Reject die sites on defective substrates of a support element are covered prior to the encapsulation process using a cover member. The cover member comprises, for example, pressure-sensitive or temperature-activated tape, reject dies, or the like. The support elements and methods of the present invention virtually eliminate bleeding or flashing during encapsulation due to the presence of reject die sites. The support elements and methods of the present invention further ensure that functional dice are not sacrificed by being attached to reject die sites, thereby decreasing manufacturing costs while increasing yield of functional semiconductor packages.

摘要翻译： 提供了包括附接到一个或多个废弃模具位置的盖构件的半导体封装支撑元件。 还提供了制造本发明的支撑元件和制造使用其的半导体封装件的方法。 在使用盖构件的封装工艺之前，覆盖支撑元件的有缺陷的基底上的模具位置。 盖构件包括例如压敏或温度活化的带，废模或类似物。 本发明的支撑元件和方法由于存在废弃模具位置而实际上消除了在封装期间的渗出或闪烁。 本发明的支撑元件和方法进一步确保功能性骰子不会被附着到废弃模具位置而牺牲，从而降低制造成本，同时提高功能性半导体封装的产量。