公开(公告)号：US20050130368A1

公开(公告)日：2005-06-16

申请号：US11048556

申请日：2005-02-01

Applicant: Kiyoshi Ooi ,  Yasuyoshi Horikawa ,  Tomoo Yamasaki

Inventor： Kiyoshi Ooi ,  Yasuyoshi Horikawa ,  Tomoo Yamasaki

IPC: H01L23/12 ,  H01G4/224 ,  H01L21/68 ,  H01L23/50 ,  H01L23/64 ,  H05K1/16 ,  H01L51/40 ,  H01L21/44 ,  H01L21/8242

CPC classification number: H01G4/224 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/642 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/162 ,  H05K2201/0162 ,  H05K2201/09763 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A capacitor includes a capacitor part formed of a dielectric film sandwiched by a pair of electrodes and a support body formed of a film of an organic polysilane. The support body is provided so as to support the capacitor part thereon.

Abstract translation: 电容器包括由夹在一对电极之间的电介质膜和由有机聚硅烷膜形成的支撑体形成的电容器部分。 支撑体设置成在其上支撑电容器部分。

公开(公告)号：US20050126820A1

公开(公告)日：2005-06-16

申请号：US11023499

申请日：2004-12-29

Applicant: Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

Inventor： Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

IPC: H05K1/09 ,  H05K1/16 ,  H05K3/40 ,  H05K3/46 ,  H05K3/30

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  H05K2203/1189 ,  Y10T29/4902 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

Abstract translation: 公开了一种具有无源元件的布线板的制造方法。 制造方法包括在第一金属箔和第二金属箔的至少一个第一表面上涂覆电阻浆料和电介质浆料中的一种或两种，每个第一表面具有第一表面和第二表面; 布置具有热塑性和热固性的绝缘板，以便面对第一金属箔的第一表面，并且将第二金属箔的第一表面侧布置成面对不同于表面的表面 绝缘板的第一金属箔面; 通过对所配置的第一金属箔，绝缘板和第二金属箔进行堆叠，加压和加热来形成双面布线板，从而将它们集成; 以及图案化第一金属箔和/或第二金属箔。

公开(公告)号：US06897544B2

公开(公告)日：2005-05-24

申请号：US10692836

申请日：2003-10-24

Applicant: Kiyoshi Ooi ,  Yasuyoshi Horikawa ,  Tomoo Yamasaki

Inventor： Kiyoshi Ooi ,  Yasuyoshi Horikawa ,  Tomoo Yamasaki

IPC: H01L23/12 ,  H01G4/224 ,  H01L21/68 ,  H01L23/50 ,  H01L23/64 ,  H05K1/16 ,  H01L27/108 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01G4/224 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/642 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/162 ,  H05K2201/0162 ,  H05K2201/09763 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05166

Abstract: A capacitor includes a capacitor part formed of a dielectric film sandwiched by a pair of electrodes and a support body formed of a film of an organic polysilane. The support body is provided so as to support the capacitor part thereon.

公开(公告)号：US06889431B2

公开(公告)日：2005-05-10

申请号：US10078448

申请日：2002-02-21

Applicant: Hiroshi Okabe ,  Hirozi Yamada ,  Eriko Takeda ,  Kazunori Yamamoto ,  Hiroyuki Kuriya ,  Masanori Yamaguchi ,  Kazuhisa Otsuka ,  Yoshitaka Hirata ,  Yasushi Shimada

Inventor： Hiroshi Okabe ,  Hirozi Yamada ,  Eriko Takeda ,  Kazunori Yamamoto ,  Hiroyuki Kuriya ,  Masanori Yamaguchi ,  Kazuhisa Otsuka ,  Yoshitaka Hirata ,  Yasushi Shimada

IPC: H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46 ,  H05K3/02

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/162 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0338 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a manufacturing method of an electronic circuit device including a multi-layer circuit board incorporated with a thin film capacitor small in size and of high performance capable of attaining higher capacitance value with a thin dielectric film of high dielectric constant and with favorable film quality. A first electrode layer and a thin film dielectric layer are laminated continuously in this order in one identical to laminate each of the layers on a leveled substrate in one identical chamber and then the first electrode layer is fabricated a conductor pattern.

Abstract translation: 本发明提供一种电子电路器件的制造方法，该电子电路器件包括多层电路板，该多层电路板结合有小型和高性能的薄膜电容器，能够用高介电常数的薄电介质膜获得较高的电容值 电影质量。 将第一电极层和薄膜电介质层依次层叠在一个相同的层中，在一个相同的室中的层叠基板上层叠，然后将第一电极层制成导体图案。

公开(公告)号：US20050013088A1

公开(公告)日：2005-01-20

申请号：US10889312

申请日：2004-07-13

Applicant: Yasuyoshi Horikawa ,  Tomoo Yamasaki ,  Kiyoshi Ooi

Inventor： Yasuyoshi Horikawa ,  Tomoo Yamasaki ,  Kiyoshi Ooi

IPC: H01G4/33 ,  H01G9/012 ,  H01G9/02 ,  H01G9/042 ,  H01L21/3205 ,  H01L21/68 ,  H01L21/822 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L27/04 ,  H05K1/11 ,  H05K1/16 ,  H05K3/20

CPC classification number: H01G9/012 ,  H01G9/042 ,  H01G9/0425 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/50 ,  H01L2221/68345 ,  H01L2224/05001 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/162 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/43 ,  H01L2924/00014

Abstract: A capacitor device of the present invention includes a substrate, a float electrode formed on the substrate, a valve metal film formed on the float electrode, a dielectric film formed on the valve metal film by applying an anodic oxidation to a part of the valve metal film, and a pair of electrodes provided in areas overlapping with two different parts of the float electrode on the dielectric film respectively.

Abstract translation: 本发明的电容器装置包括基板，形成在基板上的浮动电极，形成在浮动电极上的阀金属膜，通过对阀金属的一部分施加阳极氧化而形成在阀金属膜上的电介质膜 膜和一对电极，其分别设置在与电极上的浮动电极的两个不同部分重叠的区域中。

公开(公告)号：US20050000728A1

公开(公告)日：2005-01-06

申请号：US10879125

申请日：2004-06-30

Applicant: Koichi Tanaka

Inventor： Koichi Tanaka

IPC: H05K1/09 ,  H05K1/16 ,  H05K3/24

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K2201/0347 ,  H05K2201/09763 ,  H05K2203/1453 ,  H05K2203/171 ,  Y10T29/49098 ,  Y10T29/49099 ,  Y10T29/49155

Abstract: A wiring board provided with a resistor comprises: an insulating substrate having a surface; wiring patterns formed on the surface, the wiring patterns including first and second electrodes spaced from each other by a certain distance; a first resistor (horizontal type resistor) formed on the surface, the first resistor having respective ends connected with the first and second electrodes, respectively; the wiring patterns further including a third electrode, occupying a first plane area on the surface; a second resistor (vertical type resistor) formed on the third electrode; a fourth electrode formed on the second resistor; and the second resistor and the fourth electrode being located in a second plane area within the first plane area.

Abstract translation: 设置有电阻器的布线板包括：具有表面的绝缘基板; 布线图案形成在表面上，布线图案包括彼此隔开一定距离的第一和第二电极; 形成在所述表面上的第一电阻器（水平型电阻器），所述第一电阻器分别具有与所述第一和第二电极连接的端部; 所述布线图形还包括占据所述表面上的第一平面区域的第三电极; 形成在第三电极上的第二电阻器（垂直型电阻器） 形成在所述第二电阻器上的第四电极; 并且所述第二电阻器和所述第四电极位于所述第一平面区域内的第二平面区域中。

公开(公告)号：US06764931B2

公开(公告)日：2004-07-20

申请号：US10225305

申请日：2002-08-22

Applicant: Takahiro Iijima ,  Akio Rokugawa ,  Noriyoshi Shimizu

Inventor： Takahiro Iijima ,  Akio Rokugawa ,  Noriyoshi Shimizu

IPC: H01L2120

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  Y10S428/901

Abstract: A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.

Abstract translation: 形成用作在绝缘基底构件上以预定形状图案化的电容器部分的第一电极层的布线层。 使用电泳工艺在布线层的表面上形成用作电容器部分的介电层的树脂层。 形成另一布线层，用于通过在包括树脂层的绝缘基底上进行图案化而以预定形状图案化的电容器部分的第二电极层。

公开(公告)号：US20040087058A1

公开(公告)日：2004-05-06

申请号：US10693216

申请日：2003-10-24

Inventor： Kiyoshi Ooi ,  Yasuyoshi Horikawa

IPC: H01L021/44 ,  H01L023/02 ,  H01L029/00 ,  H01L023/48 ,  H01L021/50 ,  H01L029/40

CPC classification number: H01L21/6835 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/162 ,  H05K2201/09763 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A substrate includes a plurality of insulation layers forming a laminated structure and a built-in capacitor formed in the laminated structure, wherein the laminated structure includes a layer of baked organic polysilane.

Abstract translation: 基板包括形成叠层结构的多个绝缘层和形成在层压结构中的内置电容器，其中层压结构包括一层烘烤的有机聚硅烷。

公开(公告)号：US20040080021A1

公开(公告)日：2004-04-29

申请号：US10686116

申请日：2003-10-15

Inventor： Michael D. Casper ,  William B. Mraz

IPC: H01L029/00

CPC classification number: H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L25/16 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19011 ,  H01Q21/061 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/002 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H01L2924/00

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

公开(公告)号：US06476695B1

公开(公告)日：2002-11-05

申请号：US09578691

申请日：2000-05-26

Applicant: Masumi Nakamichi

Inventor： Masumi Nakamichi

IPC: H01P308

CPC classification number: H05K1/167 ,  H05K1/0237 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/10045 ,  H05K2203/1461

Abstract: A high frequency module is provided with a resistor array layer with interconnections, in which a plurality of resistor elements having a prescribed resistance value are formed as an array, and in which an interconnection pattern for providing electrical connection to each resistor element is formed in advance. Additionally, a capacitor array layer with interconnection in which a plurality of capacitor elements having a prescribed capacitance value are formed as an array and an interconnection pattern for providing electrical connection to each capacitor element is also formed in advance for later use. A desired circuit constant is obtained by providing interconnections among the plurality of resistor elements and among the plurality of capacitor elements, respectively, in any given combination by simply modifying the respective interconnection patterns instead of the entire module. With this configuration, a high frequency module of a more compact and lighter type which facilitates design modification is provided at a low cost.

Abstract translation: 高频模块设置有具有互连的电阻器阵列层，其中具有规定电阻值的多个电阻元件形成为阵列，并且其中预先形成用于提供与每个电阻器元件的电连接的互连图案 。 此外，具有互连的电容器阵列层，其中具有规定的电容值的多个电容器元件形成为阵列，并且还预先形成用于提供与每个电容器元件的电连接的互连图案供稍后使用。 通过仅通过简单地修改相应的互连图案而不是整个模块，分别在多个电阻元件之间和多个电容器元件之间分别提供互连来获得期望的电路常数。 利用这种配置，以低成本提供了便于设计修改的更紧凑和更轻型的高频模块。