公开(公告)号：US20110121366A1

公开(公告)日：2011-05-26

申请号：US13016313

申请日：2011-01-28

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J.L. de Jong ,  Deepak C. Sekar ,  Paul Lim

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J.L. de Jong ,  Deepak C. Sekar ,  Paul Lim

IPC: H01L27/118

CPC classification number: H01L21/8221 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes a first single crystal silicon layer including first transistors, a first alignment mark, and at least one metal layer overlying the first single crystal silicon layer for interconnecting the first transistors; a second layer overlying the at least one metal layer, wherein the second layer includes a plurality of second transistors; and a connection path connecting the first transistors and the second transistors and including at least a first strip, a second strip, and a through via connecting the first strip and the second strip, wherein the second strip is substantially orthogonal to the first strip and wherein the through via is substantially away from both ends of the first strip and both ends of the second strip.

Abstract translation: 半导体器件包括第一单晶硅层，其包括第一晶体管，第一对准标记和覆盖在第一单晶硅层上的至少一个金属层，用于互连第一晶体管; 覆盖所述至少一个金属层的第二层，其中所述第二层包括多个第二晶体管; 以及连接路径，其连接第一晶体管和第二晶体管，并且至少包括连接第一条带和第二条带的第一条带，第二条带和通孔，其中第二条带基本上与第一条带正交， 通孔基本上远离第一条带的两端和第二条带的两端。

公开(公告)号：US20110092030A1

公开(公告)日：2011-04-21

申请号：US12970602

申请日：2010-12-16

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar ,  Paul Lim

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar ,  Paul Lim

IPC: H01L21/822

CPC classification number: H01L27/1266 ,  G06F17/5072 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7848 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/80001 ,  H01L2924/00012

Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

公开(公告)号：US20110084314A1

公开(公告)日：2011-04-14

申请号：US12900379

申请日：2010-10-07

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J.L. de Jong ,  Deepak C. Sekar ,  Zeev Wurman

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J.L. de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L23/52

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Abstract translation: 系统包括半导体器件。 半导体器件包括第一单晶硅层，其包括第一晶体管，第一对准标记和覆盖在第一单晶硅层上的至少一个金属层，其中所述至少一个金属层比其它材料包括铜或铝; 以及覆盖所述至少一个金属层的第二单晶硅层。 第二单晶硅层包括以基本平行的带布置的多个第二晶体管。 多个频带中的每一个包括沿着重复图案的轴的第二晶体管的一部分。

公开(公告)号：US20110031997A1

公开(公告)日：2011-02-10

申请号：US12577532

申请日：2009-10-12

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Zeev Wurman ,  Reza Arghavani ,  Israel Beinglass

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Zeev Wurman ,  Reza Arghavani ,  Israel Beinglass

IPC: H03K19/173

CPC classification number: H03K19/17704 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/181 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the at least one antifuse.

Abstract translation: 提出了一种可用于提供可配置逻辑器件的方法，其可以是具有体积灵活性的现场可编程的。 制造集成电路的方法可以包括以下步骤：提供半导体衬底并形成无边界逻辑阵列，并且还可以包括形成多个反熔丝可配置互连电路和/或多个晶体管以在 最少一个反熔丝。 可以在至少一个反熔丝上制造编程晶体管。

公开(公告)号：US09136153B2

公开(公告)日：2015-09-15

申请号：US13492395

申请日：2012-06-08

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/16225 ,  H01L2924/00012

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 互连第一晶体管并且包括铝或铜的第一互连层; 包括第二晶体管的第二层; 其中所述第二晶体管与所述第一晶体管对准，具有小于40nm的对准误差，并且其中所述第二层覆盖所述第一互连层，并且其中所述第二晶体管中的至少一个具有背偏置结构， 至少一个第二晶体管的性能。

公开(公告)号：US08754533B2

公开(公告)日：2014-06-17

申请号：US12949617

申请日：2010-11-18

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L29/40 ,  H01L23/544 ,  H01L27/02 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L21/822 ,  H01L27/108 ,  H01L27/112 ,  H01L27/11 ,  H01L27/105 ,  H01L27/06 ,  H01L27/118 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2924/00012

Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Abstract translation: 半导体器件包括包括第一晶体管的第一单结晶层和形成第一晶体管之间的连接的至少一部分的第一金属层; 以及包括第二晶体管的第二层，所述第二晶体管包括单晶材料，所述第二层覆盖所述第一金属层，其中所述第一金属层包括铝或铜，并且其中所述第二层的厚度小于1微米，并且包括 逻辑单元。

公开(公告)号：US08541819B1

公开(公告)日：2013-09-24

申请号：US12963659

申请日：2010-12-09

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L23/528

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L24/05 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.

Abstract translation: 一种半导体器件，包括：第一单晶层和第二单晶层及其中的至少一个导电层; 其中所述至少一个导电层包括覆盖覆盖在第三导电层上的第二导电层的第一导电层，并且其中所述第二导电层具有大于所述第一导电层的载流能力的预定的第二层载流容量，以及 第二导电层电流承载能力大于第三导电层的载流能力。

公开(公告)号：US20130241026A1

公开(公告)日：2013-09-19

申请号：US13423200

申请日：2012-03-17

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/04

CPC classification number: H01L21/8221 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2224/16225 ,  H01L2224/73253

Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion.

Abstract translation: 一种包括由至少一个第一互连层互连的第一层第一晶体管的器件，其中所述第一互连层包括铜或铝，包括第二晶体管的第二层，覆盖所述第一互连层的所述第二层，其中所述第二层较少 超过2微米厚，其中第二层具有热膨胀系数; 以及将所述第二晶体管中的至少一个连接到所述第一互连层的连接路径，其中所述连接路径包括至少一个贯通层通孔，并且其中所述贯穿层通孔包括热膨胀系数在50以内的材料 百分比的第二层热膨胀系数。

公开(公告)号：US20130020707A1

公开(公告)日：2013-01-24

申请号：US13623756

申请日：2012-09-20

Applicant: Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC: H01L23/48

CPC classification number: B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC based system including: a first semiconductor layer including first alignment marks and first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer; and wherein the second transistors include a plurality of N-type transistors and P-type transistors, and wherein the second mono-crystallized semiconductor layer is transferred from a reusable donor wafer.

Abstract translation: 一种基于3D IC的系统，包括：包括第一对准标记和第一晶体管的第一半导体层，其中所述第一晶体管通过包括铝或铜的至少一个金属层互连; 包括第二晶体管并覆盖所述至少一个金属层的第二单结晶半导体层，其中所述至少一个金属层位于所述第一半导体层和所述第二单结晶半导体层之间; 并且其中所述第二晶体管包括多个N型晶体管和P型晶体管，并且其中所述第二单结晶半导体层从可重复使用的施主晶片转移。

公开(公告)号：US20120273955A1

公开(公告)日：2012-11-01

申请号：US13492382

申请日：2012-06-08

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L23/48 ,  H01L21/02

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.