公开(公告)号：US08680674B2

公开(公告)日：2014-03-25

申请号：US13485886

申请日：2012-05-31

申请人： Michael B. McShane ,  Kevin J. Hess ,  Perry H. Pelley ,  Tab A. Stephens

发明人： Michael B. McShane ,  Kevin J. Hess ,  Perry H. Pelley ,  Tab A. Stephens

IPC分类号： H01L23/34 ,  H01L23/52 ,  H01L23/48 ,  H01L23/02 ,  H01L21/48

CPC分类号： H01L23/367 ,  H01L23/13 ,  H01L23/3107 ,  H01L27/10897 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.

摘要翻译： 半导体器件包括具有顶侧和背面的集成电路（IC）模具。 电路基板包括热源电路，热敏电路，耦合到电路基板的顶侧的封装基板和从电路基板的背面形成的多个导热通硅通孔（TSV） 靠近而不是通过电路基板的顶侧。

公开(公告)号：US20120020040A1

公开(公告)日：2012-01-26

申请号：US13136185

申请日：2011-07-26

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H05K1/18

CPC分类号： H05K1/144 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K3/3436 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contact pads disposed on a top and/or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack.

摘要翻译： 本发明公开了一种用于制造包含并保护集成电路（IC）芯片的封装到封装（P2P）堆叠模块的电子封装的结构和工艺。 该方法包括提供插入件的步骤，该插入件包括在布置在顶部和/或底部表面上的预先指定的接触垫之间互连的导电迹线，用于安装IC芯片的至少顶部或底部封装，其中电气端子与设置的接触焊盘接触 在插入器的顶部和/或底部表面上。 支架和无源元件也可以添加到插入器上，以便同时提高焊点的可靠性，电气性能和主板密度。 将无源部件包含在插入器上可以增强成品封装堆叠的电性能和可测试性。

公开(公告)号：US5468999A

公开(公告)日：1995-11-21

申请号：US249602

申请日：1994-05-26

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L23/24 ,  H01L23/31 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107

摘要： A ball grid array semiconductor device (10) includes a package substrate (14 or 16) having a plurality of conductive traces (18), bond posts (20), and conductive vias (22). A semiconductor die (12) is mounted to the package substrate. Orthogonal wire bonds (28) are used to electrically connect staggered bond pads (26) to corresponding bond posts (20) on the substrate. A liquid encapsulant (40) is used to cover the die, the wire bonds, and portions of the package substrate. In another embodiment, a package substrate (50) includes a lower bonding tier (52) and an upper bonding tier (54). Wire bonds (60) are used to electrically connect an outer row of bond pads (64) to bond posts (20) of lower tier (52), while wire bonds (62) are used to electrically connect an inner row of bond pads (64) to bond posts (20) of an upper tier (54). The loop height of wire bonds (60) is smaller than that of wire bonds (62).

摘要翻译： 球栅阵列半导体器件（10）包括具有多个导电迹线（18），接合柱（20）和导电通孔（22）的封装衬底（14或16）。 半导体管芯（12）安装到封装衬底上。 正交线接合（28）用于将交错的接合焊盘（26）电连接到衬底上的对应的接合柱（20）。 液体密封剂（40）用于覆盖模具，引线键合和封装衬底的部分。 在另一个实施例中，封装衬底（50）包括下结合层（52）和上结合层（54）。 线接合（60）用于将外排的接合焊盘（64）电连接到下层（52）的接合柱（20），而引线接合（62）用于电连接内排接合焊盘 64）到上层（54）的粘合柱（20）。 引线键（60）的环路高度小于引线键合（62）。

公开(公告)号：US5273938A

公开(公告)日：1993-12-28

申请号：US876315

申请日：1992-04-30

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/498 ,  H05K3/34 ,  H01L21/28 ,  H01L21/60 ,  H01L21/70

CPC分类号： H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49855 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K3/3431 ,  Y10T29/49146

摘要： A low cost manufacturing method is used to fabricate a small multichip semiconductor device (30). In one embodiment, a pattern of conductive traces (13) is formed on a film of transfer material (12). A first semiconductor die (15) is interconnected to the traces and a resin body (20) is formed around the first die and one side of the traces. The film of transfer material forms, at this stage of the process, one side of the first package. The film of transfer material is then peeled from the pattern of conductive traces and the first resin body to expose the other side of the traces. A second semiconductor die (23) is interconnected to the exposed side of the traces. A second resin body (25) is formed around the second die and portions of the exposed traces. Solder balls (26) are coupled to the exposed portions of the traces to establish external electrical connections to each die.

摘要翻译： 使用低成本制造方法来制造小型多芯片半导体器件（30）。 在一个实施例中，导电迹线（13）的图案形成在转印材料（12）的膜上。 第一半导体管芯（15）与迹线相互连接，树脂体（20）围绕第一管芯和迹线的一侧形成。 在该过程的这个阶段，转印材料的薄膜形成第一包装的一面。 然后将转印材料的膜从导电迹线图案和第一树脂体的图案剥离，以露出迹线的另一侧。 第二半导体管芯（23）与迹线的暴露侧相互连接。 第二树脂体（25）围绕第二管芯和暴露的迹线的一部分形成。 焊球（26）耦合到迹线的暴露部分以建立到每个管芯的外部电连接。

公开(公告)号：US5216278A

公开(公告)日：1993-06-01

申请号：US841765

申请日：1992-03-02

申请人： Paul T. Lin ,  Michael B. McShane ,  Howard P. Wilson

发明人： Paul T. Lin ,  Michael B. McShane ,  Howard P. Wilson

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L23/49827 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011

摘要： A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.

摘要翻译： 一种半导体器件（10），其具有通过形成在所述载体衬底（12）中的通孔（32）互连的载体衬底（12）的相对表面上的第一和第二布线层（30,33），所述通孔（32）将电子部件（18）电耦合到 通过从通孔（32）移开的柔性焊球（26）的安装基板，所述半导体器件（10）的特征在于具有高性能电气封装互连（24）和良好散热的标准尺寸的载体衬底（12）。 通过提供独立的布线层（30,33）来获得改善的电性能，每个独立布线层具有专门为特定的电子部件（18）设计的引线迹线布局和特定的板连接要求，同时使用标准尺寸封装轮廓。 通过在能够支撑本身具有不同尺寸的各种不同的电子部件（18）的标准尺寸的载体基板（12）上提供塑料封装模具（36）来减少装配成本。

公开(公告)号：US5045914A

公开(公告)日：1991-09-03

申请号：US663225

申请日：1991-03-01

申请人： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

发明人： James J. Casto ,  Michael B. McShane ,  Paul T. Lin

IPC分类号： H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L25/10 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49517 ,  H01L23/49589 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/09709 ,  H05K2201/10515 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H05K2201/10931 ,  H05K2201/2036 ,  H05K3/3426 ,  Y02P70/613

摘要： A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure. The periphery of the package body may function as a carrier structure to protect the lead or connection structures during testing, handling and board mounting. The open vias permit back side testing of the device before or after mounting of the package to the PCB. Additionally, a heat sink structure and/or capacitor may be directly bonded to the side or the top of the pad array electronic device which may be used singly or in multiple, stacked configurations, to facilitate the thermal dissipation from the device.

摘要翻译： 用于安装在诸如印刷电路板（PCB）的基板上的焊盘阵列电子器件具有相对刚性的封装体，其具有多个孔，该多个孔承载用于结合到PCB上的焊盘的连接机构。 封装体可以是可以围绕电子部件注射模制的热固性塑料或其它材料，例如结合到引线框架的集成电路（IC）。 集成电路芯片或其他电子部件安装在引线框架附近或之上，并且通过任何常规方式制造集成电路芯片和框架之间的电连接。 在一个方面，衬底引线设置在其外端处，其被封装中的孔暴露以用于与PCB连接的焊球或焊盘。 封装体可以可选地用于从PCB离开设备一定距离，使得焊球将形成适当的凹形结构。 封装主体的周边可以用作载体结构，以在测试，处理和板安装期间保护引线或连接结构。 打开的通孔允许在将封装安装到PCB之前或之后对器件进行背面测试。 此外，散热器结构和/或电容器可以直接结合到可以单独使用或以多个堆叠配置使用的焊盘阵列电子器件的侧面或顶部，以便于从器件散热。

公开(公告)号：US5041902A

公开(公告)日：1991-08-20

申请号：US450763

申请日：1989-12-14

申请人： Michael B. McShane

发明人： Michael B. McShane

IPC分类号： H01L23/367 ,  H01L23/433 ,  H01L23/495

CPC分类号： H01L23/49551 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49541 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/30107

摘要： A molded package having reduced unintentional and undesirable mold flash or bleed around an exposed heat sink is provided through the use of a compression structure within the package. The compression structure may be integral with a heat sink, die bond flag, if one is present, or may be a separate structure, which extends from a die support surface of the heat sink to the opposite side of the mold. During molding, the compression structure presses a heat dissipation surface of the heat sink against the mold surface forming a tight seal to prevent the mold compound from creeping around between the mold and the heat dissipation surface to form flash. The heat sink may also be provided with adhesion promotion features along its side to improve the physical bond or attachment between the heat sink and the plastic body of the package.

摘要翻译： 通过使用包装内的压缩结构，提供了具有减少的无意且不期望的模具闪光或围绕暴露的散热器流出的模制包装。 压缩结构可以与散热器，管芯接合标记（如果存在）成一体，或者可以是从散热片的模具支撑表面延伸到模具的相对侧的单独的结构。 在模制期间，压缩结构将散热器的散热表面压在模具表面上，形成紧密的密封，以防止模具化合物在模具和散热表面之间蠕变形成闪光。 散热器也可以沿着其侧面设置有粘附促进特征，以改善散热器与包装体的塑料体之间的物理接合或附着。

公开(公告)号：US5018005A

公开(公告)日：1991-05-21

申请号：US457648

申请日：1989-12-27

申请人： Paul T. Lin ,  Michael B. McShane

发明人： Paul T. Lin ,  Michael B. McShane

IPC分类号： H01L23/50 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30

CPC分类号： H01L22/00 ,  H01L23/3121 ,  H01L23/4985 ,  H05K3/303 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K2201/10303 ,  H05K2201/10681 ,  H05K2203/167 ,  Y02P70/613

摘要： An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternate version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process. The periphery and test points may be sheared away before the package is mounted to the PCB. A variety of outer bonding area pitches may be provided on the same package with test points of a standard pitch. The relatively inexpensive device is thin and easily mounted by conventional techniques.

公开(公告)号：US09076664B2

公开(公告)日：2015-07-07

申请号：US13268580

申请日：2011-10-07

申请人： Perry H. Pelley ,  Kevin J. Hess ,  Michael B. McShane

发明人： Perry H. Pelley ,  Kevin J. Hess ,  Michael B. McShane

IPC分类号： H01L23/48 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06589

摘要： A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.

摘要翻译： 叠层半导体器件包括第一，第二，第三和第四半导体器件。 每个第一和第二半导体器件的第一主表面包括有源电路直接面对彼此，第三和第四半导体器件的第一主表面包括有源电路直接面对彼此。 第二半导体器件的第二主表面直接面向第三半导体器件的第二主表面。 堆叠的半导体器件包括多个连续的导电通孔，其中每个连续导电通孔从第一器件的第二主表面延伸穿过第一器件，第二器件，第三器件和第四器件到第四器件的第二主表面 设备。 每个半导体器件可以包括在器件的至少一个边缘上的第一主表面处的倾斜边缘。

公开(公告)号：US08957510B2

公开(公告)日：2015-02-17

申请号：US13935015

申请日：2013-07-03

申请人： Tim V. Pham ,  James R. Guajardo ,  Michael B. McShane

发明人： Tim V. Pham ,  James R. Guajardo ,  Michael B. McShane

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/16245 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.

摘要翻译： 半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的半导体管芯，第一次表面和与第一次表面相对的第二次表面，在第一主表面上的多个接触焊盘，以及 从第一次表面和第二主表面延伸到半导体管芯中的凹口。 所述凹口具有从所述第二主表面测量到所述半导体管芯中的切口深度，其中所述凹口深度小于所述半导体管芯的厚度，以及从所述第一次表面到所述半导体管芯中测量的切口长度，其中所述切口长度 小于在第一和第二次表面之间测量的半导体管芯的长度。 所述装置包括具有在所述凹口中的第一端的引线和在所述第一主表面上的密封剂。