公开(公告)号：US20190096861A1

公开(公告)日：2019-03-28

申请号：US16201569

申请日：2018-11-27

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Ashok S. Prabhu

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/60 ,  H01L21/56

Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.

公开(公告)号：US09991233B2

公开(公告)日：2018-06-05

申请号：US15393100

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/52

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.

公开(公告)号：US20180026018A1

公开(公告)日：2018-01-25

申请号：US15393083

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/10 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.

公开(公告)号：US20170141083A1

公开(公告)日：2017-05-18

申请号：US15353577

申请日：2016-11-16

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/48 ,  H01L21/288 ,  H01L25/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/54 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3511

Abstract: Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. A microelectronic device is coupled in an inner region of the packaged microelectronic device inside the outer region. A dielectric layer surrounds at least portions of shafts of the interconnect structures and along sides of the microelectronic device. The interconnect structures have first ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.

公开(公告)号：US20170117260A1

公开(公告)日：2017-04-27

申请号：US15332991

申请日：2016-10-24

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/4846 ,  H01L21/4885 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/02 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L2021/60 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.

公开(公告)号：US20170117231A1

公开(公告)日：2017-04-27

申请号：US15344990

申请日：2016-11-07

Applicant: Invensas Corporation

Inventor： Abiola Awujoola ,  Zhuowen Sun ,  Wael Zohni ,  Ashok S. Prabhu ,  Willmar Subido

IPC: H01L23/552 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4942 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

公开(公告)号：US20170077016A1

公开(公告)日：2017-03-16

申请号：US15342744

申请日：2016-11-03

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar ,  Sean Moran

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/29 ,  H01L23/552

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24175 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

Abstract translation: 组件包括多个堆叠的封装的微电子封装，每个封装包括微电子元件，该微电子元件具有在前表面处具有多个芯片触点的前表面和远离前表面延伸的边缘表面。 每个包装的封装区域接触至少一个边缘表面，并从其延伸到包装的远端表面。 每个封装的封装触点设置在远程表面中的单个一个处，封装触点面对并与衬底的与其中的微电子元件的前表面不平行的表面处的相应触点耦合。

公开(公告)号：US20170018485A1

公开(公告)日：2017-01-19

申请号：US15209034

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh

IPC: H01L23/495 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49541 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/18

Abstract: A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.

Abstract translation: 微电子组件包括一组微电子元件，例如半导体芯片，每个半导体芯片具有限定多个平面的相应平面的前表面。 连接到每个芯片的前表面处的触点的引线框互连可以延伸到超过相应微电子元件的边缘表面的位置。 芯片堆叠以一定角度安装到支撑元件，使得芯片的边缘表​​面面向支撑元件的主表面，该主表面限定横向于，即不平行于多个平行平面的第二平面。 引线框互连在其端部电耦合到支撑元件的表面处的相应触点。