公开(公告)号：US20130087920A1

公开(公告)日：2013-04-11

申请号：US13270776

申请日：2011-10-11

Applicant: Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Shin-Puu Jeng ,  Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L23/488 ,  H01L21/50

CPC classification number: H01L24/16 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16258 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/05552

Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.

Abstract translation: 实施例是包括基板，第一模具和第二模具的结构。 衬底具有第一表面。 第一模具通过第一电连接器附接到基板的第一表面。 第二模具通过第二电连接器附接到基板的第一表面。 第二电连接器之一的尺寸小于第一电连接器之一的尺寸。

公开(公告)号：US20130056865A1

公开(公告)日：2013-03-07

申请号：US13224575

申请日：2011-09-02

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/78 ,  H01L23/498

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

Abstract: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US20130037990A1

公开(公告)日：2013-02-14

申请号：US13208197

申请日：2011-08-11

Applicant: Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/56

CPC classification number: H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

Abstract translation: 模制系统的底部追逐和顶部追逐形成容纳模制载体和一个或多个装置的空腔。 模制载体被放置在由引导部件限定的期望位置。 引导部件可以完全在腔内，或者延伸到底部追逐的表面之上，并延伸到顶部追逐和底部追逐的接触边缘上，使得在顶部追逐的边缘和边缘之间存在间隙 由模制材料填充以覆盖模制载体的边缘的模制载体。 释放部件可以与顶部追逐和/或底部追逐相关联，其可以是具有释放膜的多个带辊或底部追逐内的多个真空孔，或者具有底部追逐的多个底部销 。

公开(公告)号：US08338884B2

公开(公告)日：2012-12-25

申请号：US12708711

申请日：2010-02-19

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/00

CPC classification number: H01L21/02494 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/267

Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.

Abstract translation: 半导体器件包括由第一半导体材料形成的衬底; 基板上有两个绝缘子; 以及半导体区域，其具有在所述两个绝缘体之间并且在所述衬底上的部分。 半导体区域具有与衬底接触并具有倾斜侧壁的底表面。 半导体区域由与第一半导体材料不同的第二半导体材料形成。

公开(公告)号：US20120238057A1

公开(公告)日：2012-09-20

申请号：US13488188

申请日：2012-06-04

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC: H01L21/60

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

公开(公告)号：US20120028411A1

公开(公告)日：2012-02-02

申请号：US12880736

申请日：2010-09-13

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L21/50

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/568 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/13 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.

Abstract translation: 一种方法包括提供载体上设置有粘合层; 以及提供包括第一表面，与第一表面相对的第二表面的模具。 模具还包括与第二表面相邻的多个接合焊盘; 以及多个接合焊盘上的介电层。 该方法还包括将模具放置在粘合剂层上，其中第一表面面向粘合剂层，电介质层背向粘合剂层; 形成模塑料以覆盖模具，其中模塑料围绕模具; 将模塑料的一部分直接在模具上去除以暴露介电层; 以及在所述模制化合物上形成再分配线，并通过所述介电层电耦合到所述多个键合焊盘之一。

公开(公告)号：US20110316147A1

公开(公告)日：2011-12-29

申请号：US12823851

申请日：2010-06-25

Applicant: Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/488

CPC classification number: H01L21/76885 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4007 ,  H05K2203/016 ,  H05K2203/025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/16145 ,  H01L2924/00012

Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

Abstract translation: 一种装置包括：插入件，其包括基板; 以及衬底上的至少一个电介质层。 多个穿通基板通孔（TSV）穿透基板。 第一金属凸块在至少一个电介质层中并电耦合到多个TSV。 第二金属凸块在至少一个电介质层的上方。 模具嵌入在至少一个电介质层中并结合到第一金属凸块。

公开(公告)号：US20110304999A1

公开(公告)日：2011-12-15

申请号：US12834943

申请日：2010-07-13

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H05K1/18 ,  H05K3/00 ,  H05K1/11

CPC classification number: H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15321 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A device includes an interposer including a substrate, and a first through-substrate via (TSV) penetrating through the substrate. A glass substrate is bonded to the interposer through a fusion bonding. The glass substrate includes a second TSV therein and electrically coupled to the first TSV.

Abstract translation: 一种器件包括内插器，其包括衬底和穿透衬底的第一穿透衬底通孔（TSV）。 玻璃基板通过熔接结合到插入件上。 玻璃基板在其中包括第二TSV并且电耦合到第一TSV。

公开(公告)号：US20110254160A1

公开(公告)日：2011-10-20

申请号：US12762085

申请日：2010-04-16

Applicant: Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Po-Hao Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538

CPC classification number: H01L23/3121 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

Abstract translation: 一种器件包括具有顶表面和底表面的衬底的插入器。 多个穿通基板通孔（TSV）穿过基板。 多个TSV包括具有第一长度和第一水平尺寸的第一TSV和具有不同于第一长度的第二长度的第二TSV和与第一水平尺寸不同的第二水平尺寸。 互连结构形成在衬底的顶表面上并电耦合到多个TSV。

公开(公告)号：US20100068873A1

公开(公告)日：2010-03-18

申请号：US12211546

申请日：2008-09-16

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/22

CPC classification number: H01L21/823842 ,  H01L21/2254 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/6659

Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

Abstract translation: 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。