公开(公告)号：US09425134B2

公开(公告)日：2016-08-23

申请号：US14339323

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  G06K9/00 ,  H01L25/065 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/49805 ,  G06K9/00006 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有上表面，下表面和侧壁的芯片。 芯片包括感测区域或器件区域以及与上表面相邻的信号焊盘区域。 浅凹陷结构位于信号垫区域的外侧，并且沿着侧壁从上表面向下表面延伸。 浅凹部结构在第一凹部下方具有至少第一凹部和第二凹部。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线的第一端位于浅凹陷结构中，并且电连接到再分配层。 电线的第二端用于外部电气连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09406818B2

公开(公告)日：2016-08-02

申请号：US14971395

申请日：2015-12-16

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Po-Han Lee

IPC: H01L23/00 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

Abstract: A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.

Abstract translation: 制造芯片封装的方法包括提供具有多个半导体芯片的半导体晶片。 在半导体晶片上形成有外隔离物和多个内隔离物。 保护盖形成并设置在外隔离件和内间隔件上。 从其下表面在每个半导体芯片上形成多个空腔，以露出设置在半导体芯片的上表面上的导电焊盘。 形成多个导电部分，并填充每个空腔并电连接到每个导电焊盘。 多个焊球设置在下表面并电连接到每个导电部分。 半导体芯片通过沿着每个半导体芯片之间的多个切割线进行切割来分离。

公开(公告)号：US09331024B2

公开(公告)日：2016-05-03

申请号：US14092795

申请日：2013-11-27

Applicant: XINTEC INC.

Inventor： Yao-Hsiang Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho ,  Shu-Ming Chang

IPC: H01L23/552 ,  H01L21/71 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/71 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06155 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic shielding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract translation: IC晶片和IC晶片的制造方法，IC晶片包括具有多个焊盘和设置在其上的绝缘层的集成电路层，多个贯穿相应于焊盘的绝缘层的通孔，分别用于 封装层的注入，以及形成在绝缘层的顶表面上并与用于电磁屏蔽的集成电路层的焊盘电隔离的电磁屏蔽层。 因此，集成电路不需要任何进一步的屏蔽掩模，从而简化制造。 此外，通孔的设计有助于进一步的包装过程。

公开(公告)号：US08779558B2

公开(公告)日：2014-07-15

申请号：US13829802

申请日：2013-03-14

Applicant: Xintec Inc.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US08728871B2

公开(公告)日：2014-05-20

申请号：US13673656

申请日：2012-11-09

Applicant: Xintec Inc.

Inventor： Wei-Ming Chen ,  Shu-Ming Chang

IPC: H01L21/00

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/83

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 封装包括载体衬底，至少两个半导体芯片，填充材料层，保护层和多个导电凸块。 载体基板包括接地区域。 半导体芯片设置在载体基板的接地区域上。 每个半导体芯片包括至少一个信号焊盘，并且包括电连接到接地区域的至少一个接地焊盘。 填充材料层形成在载体衬底上并覆盖半导体芯片。 保护层覆盖填充层。 多个导电凸块设置在保护层的上方并与半导体芯片电连接。 还公开了芯片封装的制造方法。

公开(公告)号：US08643198B2

公开(公告)日：2014-02-04

申请号：US13741318

申请日：2013-01-14

Applicant: Xintec Inc.

Inventor： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC: B05D1/36

CPC classification number: B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract translation: 本发明的实施例提供了一种形成电子器件封装的方法，该方法包括提供具有上表面和相对下表面的载体衬底; 从所述载体基板的上表面形成空腔; 将具有导电电极的电子设备设置在空腔中; 在所述空腔中形成填充层，其中所述填充层围绕所述电子设备; 将载体基板从下表面变薄到预定厚度; 在电子设备或载体衬底中形成至少一个通孔; 以及在所述通孔的侧壁上形成导电层，其中所述导电层与所述导电电极电连接。

公开(公告)号：US11746003B2

公开(公告)日：2023-09-05

申请号：US17711067

申请日：2022-04-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Chaung-Lin Lai ,  Shu-Ming Chang

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B7/0074 ,  B81C1/00301 ,  B81B2207/07

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US11521938B2

公开(公告)日：2022-12-06

申请号：US17140964

申请日：2021-01-04

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/552 ,  H01L23/528 ,  H01L23/66 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

公开(公告)号：US10049252B2

公开(公告)日：2018-08-14

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Hsing-Lung Shen

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498 ,  G06F3/041

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

公开(公告)号：US09640488B2

公开(公告)日：2017-05-02

申请号：US15008202

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Yi-Min Lin ,  Yi-Ming Chang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L29/06 ,  H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.