Patent search cpc:"H01L2225/1023" Page 4

31.

发明授权
Semiconductor chip 有权

公开(公告)号：US11798906B2

公开(公告)日：2023-10-24

申请号：US17551548

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin , Nae-in Lee , Jum-yong Park , Jin-ho Chun , Seong-min Son , Ho-Jin Lee

IPC: H01L23/00 , H01L23/31 , H01L25/10 , H01L25/065

CPC classification number: H01L24/05 , H01L23/3157 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/105 , H01L2224/0221 , H01L2224/02126 , H01L2224/02206 , H01L2224/02215 , H01L2224/02335 , H01L2224/0401 , H01L2224/05025 , H01L2224/05564 , H01L2224/11849 , H01L2224/13013 , H01L2224/13025 , H01L2224/13026 , H01L2224/13101 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2924/10253 , H01L2924/1432 , H01L2924/1434 , H01L2924/1438 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2224/13101 , H01L2924/014 , H01L2924/00014 , H01L2224/13144 , H01L2924/00014 , H01L2224/13147 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

32.

发明公开
PACKAGE STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开

公开(公告)号：US20230307338A1

公开(公告)日：2023-09-28

申请号：US17706313

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Tung Yu , Chia-Hsiang Lin , Chi-Pu Lin , Shin-Puu Jeng

IPC: H01L23/498 , H01L23/00 , H01L25/065 , H01L25/10 , H01L21/48

CPC classification number: H01L23/49822 , H01L24/73 , H01L24/16 , H01L24/32 , H01L25/0655 , H01L25/105 , H01L21/4857 , H01L21/486 , H01L23/49833 , H01L23/49838 , H01L23/49894 , H01L24/24 , H01L2224/24226 , H01L2224/73204 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/0651 , H01L2225/06548 , H01L2225/06568 , H01L23/49816

Abstract: A method includes forming a redistribution structure, wherein forming the redistribution structure includes forming a first conductive material on a portion of a first seed layer, forming a mask over the first seed layer and the first conductive material, wherein an opening in the mask at least partially exposes the first conductive material, forming a first conductive via in the opening, etching portions of the first seed layer using the first conductive material as an etching mask, depositing a first insulating layer over the first conductive via, the first conductive material and remaining portions of the first seed layer, and etching the first insulating layer such that a portion of the first conductive via protrudes above a top surface of the first insulating layer, and attaching a first die to the redistribution structure using first electrical connectors.

33.

发明授权
Architecture for computing system package 有权

公开(公告)号：US11769731B2

公开(公告)日：2023-09-26

申请号：US17229322

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu , Chieh-Yen Chen , Chuei-Tang Wang , Chung-Hao Tsai

IPC: H01L23/538 , H01L25/10 , H01L23/498 , H01L21/48 , H01L23/48 , H01L23/00

CPC classification number: H01L23/5381 , H01L21/486 , H01L21/4857 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L23/5386 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/16146 , H01L2224/16165 , H01L2224/818 , H01L2225/1023 , H01L2225/1058 , H01L2924/1431 , H01L2924/1434 , H01L2924/182

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

34.

发明授权
Semiconductor package including a redistribution structure 有权

公开(公告)号：US11735571B2

公开(公告)日：2023-08-22

申请号：US17321906

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L23/495 , H01L25/10 , H01L23/538 , H01L23/498

CPC classification number: H01L25/105 , H01L23/49838 , H01L23/5383 , H01L23/5389 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058

Abstract: A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.

35.

发明授权
Semiconductor package and method of fabricating the same 有权

公开(公告)号：US11728230B2

公开(公告)日：2023-08-15

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim , Dongho Kim , Jin-Woo Park , Jongbo Shim

IPC: H01L23/13 , H01L25/10 , H01L25/00 , H01L21/48

CPC classification number: H01L23/13 , H01L21/4853 , H01L25/105 , H01L25/50 , H01L2225/1023 , H01L2225/1058

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

36.

发明授权
Manufacturing method of semiconductor device 有权

公开(公告)号：US11721560B2

公开(公告)日：2023-08-08

申请号：US17402595

申请日：2021-08-15

Applicant: InnoLux Corporation

Inventor： Chia-Chieh Fan , Chin-Lung Ting , Cheng-Chi Wang , Ming-Tsang Wu

IPC: H01L21/56 , H01L21/48 , H01L23/00 , H01L25/00 , H01L21/683 , H01L23/31 , H01L25/10

CPC classification number: H01L21/568 , H01L21/4853 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L24/97 , H01L25/50 , H01L23/3128 , H01L25/105 , H01L2221/68345 , H01L2221/68359 , H01L2224/0231 , H01L2224/0233 , H01L2224/12105 , H01L2224/95001 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/18162 , H01L2924/3511

Abstract: A manufacturing method of semiconductor device includes providing a substrate, forming a sacrificial layer on the substrate, forming a resin layer on the sacrificial layer, disposing first chips on the sacrificial layer, and forming a first dielectric layer having trenches and surrounding the first chips, wherein an upper surface of the first dielectric layer and an upper surface of the resin layer are at a same plane.

37.

发明公开
STACK PACKAGE AND METHODS OF MANUFACTURING THE SAME 审中-公开

公开(公告)号：US20230245902A1

公开(公告)日：2023-08-03

申请号：US18132650

申请日：2023-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-in Won , Jong-kak Jang , Dong-woo Kang , Do-yeon Kim

IPC: H01L21/56 , H01L25/065 , H01L25/00 , H01L23/498 , H01L23/00 , H01L25/10

CPC classification number: H01L21/563 , H01L25/0657 , H01L25/50 , H01L21/565 , H01L23/49816 , H01L24/45 , H01L25/105 , H01L2225/06517 , H01L24/16 , H01L2224/16225 , H01L2225/0652 , H01L23/49811 , H01L2224/131 , H01L2924/1436 , H01L2224/16227 , H01L2924/1437 , H01L2924/15311 , H01L25/0655 , H01L2224/45671 , H01L2924/1533 , H01L2224/45664 , H01L2224/13111 , H01L2224/48091 , H01L2224/4568 , H01L2224/45139 , H01L2224/45678 , H01L2224/32225 , H01L2224/92125 , H01L24/13 , H01L2224/45666 , H01L2224/45669 , H01L2924/15321 , H01L24/73 , H01L2924/1438 , H01L2224/73204 , H01L24/32 , H01L2224/45147 , H01L2224/45684 , H01L2924/1434 , H01L2924/1432 , H01L2224/48227 , H01L2225/1023 , H01L24/48 , H01L24/92 , H01L2224/45144 , H01L2225/1058

Abstract: A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.

38.

发明授权
Interposer frame and method of manufacturing the same 有权

公开(公告)号：US11699691B2

公开(公告)日：2023-07-11

申请号：US16953871

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu

IPC: H01L25/10 , H01L23/538 , H01L23/14 , H01L23/498 , H01L21/48 , H01L25/00 , H01L23/31 , H01L21/56

CPC classification number: H01L25/105 , H01L21/4803 , H01L21/4846 , H01L21/563 , H01L23/14 , H01L23/145 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/49866 , H01L23/5384 , H01L23/5385 , H01L25/50 , H01L23/147 , H01L2224/16225 , H01L2224/32225 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1305 , H01L2924/13091 , H01L2924/15321 , H01L2924/13091 , H01L2924/00 , H01L2924/1305 , H01L2924/00

Abstract: Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.

39.

发明公开
PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

公开(公告)号：US20230187366A1

公开(公告)日：2023-06-15

申请号：US18077149

申请日：2022-12-07

Applicant: JCET GROUP CO., LTD.

Inventor： YAOJIAN LIN , DANFENG YANG , CHEN XU , SHUO LIU , CHENYE HE , SHASHA ZHOU , XUEQING CHEN

IPC: H01L23/538 , H01L25/16 , H01L25/10 , H01L25/065 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/29 , H01L23/498

CPC classification number: H01L23/5385 , H01L25/162 , H01L25/165 , H01L25/105 , H01L25/0655 , H01L24/16 , H01L24/32 , H01L24/73 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/563 , H01L23/3128 , H01L23/3135 , H01L23/293 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L2225/1023 , H01L2225/1041 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/19011 , H01L2924/182 , H01L2224/16227 , H01L2224/16238 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L23/49816

Abstract: The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a lower package, an upper package and a first redistribution stack layer disposed between the lower package and the upper package, wherein the first redistribution stack layer is electrically connected to the lower package and the upper package; the lower package includes a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; and the minimum line width/line spacing of the first redistribution stack layer is less than the minimum line width/line spacing of the prefabricated substrate. The lower package includes the prefabricated substrate and the first redistribution stack layer is disposed above the prefabricated substrate and has the minimum line width/line spacing less than that of the prefabricated substrate, so that more chips and/or device packages are integrated in the packaging structure.