公开(公告)号：US20150192615A1

公开(公告)日：2015-07-09

申请号：US14664220

申请日：2015-03-20

Applicant: FormFactor, Inc.

Inventor： January Kister

IPC: G01R1/073

CPC classification number: G01R1/073 ,  G01R1/06716 ,  G01R1/06733 ,  G01R1/06761 ,  G01R1/07357

Abstract: The present invention is a probe array for testing an electrical device under test comprising one or more ground/power probes and one or more signal probes and optionally a gas flow apparatus.

Abstract translation: 本发明是用于测试包括一个或多个接地/功率探针和一个或多个信号探针以及任选的气流装置的被测电气装置的探针阵列。

公开(公告)号：US20140118016A1

公开(公告)日：2014-05-01

申请号：US13665247

申请日：2012-10-31

Applicant: FORMFACTOR, INC.

Inventor： Keith J. Breinlinger ,  Kevin J. Hughes

IPC: G01R31/20

CPC classification number: G01R1/06705 ,  G01R1/06733 ,  G01R1/06738 ,  G01R1/07314 ,  G01R1/07357

Abstract: Elongated flexible probes can be disposed in holes of upper and lower guide plates of a probe card assembly. Each probe can include one or more spring mechanisms that exert normal forces against sidewalls of holes in one of the guide plates. The normal forces can result in frictional forces against the sidewalls that are substantially parallel to the sidewalls. The frictional forces can reduce or impede movement parallel to the sidewalls of the probes in the holes.

Abstract translation: 细长的柔性探针可以设置在探针卡组件的上导向板和下导板的孔中。 每个探针可以包括一个或多个弹簧机构，其在一个导板中的孔的侧壁施加法向力。 法向力可导致基本上平行于侧壁的侧壁的摩擦力。 摩擦力可以减小或妨碍平行于孔中的探针侧壁的运动。

公开(公告)号：US20130103338A1

公开(公告)日：2013-04-25

申请号：US13673111

申请日：2012-11-09

Applicant: FORMFACTOR, INC.

Inventor： Richard James Casler, JR. ,  Fenglei Du ,  Stephen Craig Fullerton

IPC: G05B13/04

CPC classification number: G05B13/048 ,  G01R31/2891 ,  H01L22/20

Abstract: An improved method and apparatus for automatically aligning probe pins to the test or bond pads of semiconductor devices under changing conditions. In at least one embodiment, a dynamic model is used to predict an impact of changing conditions to wafer probing process. This reduces the need for frequent measurements and calibrations during probing and testing, thereby increasing the number of dice that can be probed and tested in a given period of time and increasing the accuracy of probing at the same time. Embodiments of the present invention also make it possible to adjust positions of probe pins and pads in response to the changing conditions while they are in contact with each other.

Abstract translation: 一种改进的方法和装置，用于在变化的条件下将探针引脚自动对准半导体器件的测试或接合焊盘。 在至少一个实施例中，使用动态模型来预测改变条件对晶片探测过程的影响。 这减少了在探测和测试期间频繁测量和校准的需要，从而增加了在给定时间段内可以探测和测试的骰子的数量，同时提高了探测的准确性。 本发明的实施例还使得可以在彼此接触的同时响应于变化条件来调整探针和焊盘的位置。

公开(公告)号：US20040163252A1

公开(公告)日：2004-08-26

申请号：US10692114

申请日：2003-10-23

Applicant: FormFactor, Inc.

Inventor： Igor Y. Khandros ,  Benjamin N. Eldridge ,  Gaetan L. Mathieu ,  Thomas H. Dozier II ,  William D. Smith

IPC: H01R043/20 ,  H05K001/00 ,  G01R001/00

CPC classification number: H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/06716 ,  G01R1/07342 ,  G01R1/07378 ,  G01R3/00 ,  G01R31/2884 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49208 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/48

Abstract: An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure.

Abstract translation: 一种互连装置和形成互连装置的方法。 接触结构附着在第一基底上或形成在第一基底上。 第一衬底附接到比第一衬底大的第二衬底。 可以将多个这样的第一基板附接到第二基板，以便产生接触结构的阵列。 每个接触结构可以是细长的和弹性的，并且可以包括在涂覆有向接触结构赋予期望的结构特性的材料的芯上。

公开(公告)号：US20040148122A1

公开(公告)日：2004-07-29

申请号：US10756477

申请日：2004-01-12

Applicant: FormFactor, Inc.

Inventor： Ralph G. Whitten ,  Benjamin N. Eldridge

IPC: G06F019/00

CPC classification number: G01R31/3167

Abstract: Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.

公开(公告)号：US20040099641A1

公开(公告)日：2004-05-27

申请号：US10302969

申请日：2002-11-25

Applicant: FormFactor, Inc.

Inventor： Gaetan L. Mathieu ,  Benjamin N. Eldridge ,  Gary W. Grube

IPC: B23H001/00 ,  B23H009/00

CPC classification number: B23H9/00 ,  G01R1/07314

Abstract: A method of forming a probe array includes forming a layer of tip material over a block of probe material. A first electron discharge machine (EDM) electrode is positioned over the layer of tip material, the EDM electrode having a plurality of openings corresponding to a plurality of probes to be formed. Excess material from the layer of tip material and the block of probe material is removed to form the plurality of probes. A substrate having a plurality of through holes corresponding to the plurality of probes is positioned so that the probes penetrate the plurality of through holes. The substrate is bonded to the plurality of probes. Excess probe material is removed so as to planarize the substrate.

Abstract translation: 形成探针阵列的方法包括在探针材料块上形成尖端材料层。 第一电子放电机（EDM）电极位于尖端材料层上方，EDM电极具有与要形成的多个探针对应的多个开口。 去除从尖端材料层和探针材料块的多余材料以形成多个探针。 具有对应于多个探针的多个通孔的基板被定位成使得探针穿透多个通孔。 衬底被结合到多个探针。 去除过量的探针材料以使基底平坦化。

公开(公告)号：US20040064941A1

公开(公告)日：2004-04-08

申请号：US10673691

申请日：2003-09-29

Applicant: FormFactor, Inc.

Inventor： Thomas H. Dozier II ,  Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu ,  David V. Pedersen ,  Michael A. Stadt

IPC: H05K001/16 ,  H05K001/11

CPC classification number: G01R1/0408 ,  B23K3/087 ,  G01R1/0416 ,  G01R1/0466 ,  G01R31/2886 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/73251 ,  H01L2224/8114 ,  H01L2224/81901 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/119 ,  H05K3/308 ,  H05K3/325 ,  H05K2201/0311 ,  H05K2201/09472 ,  H05K2201/09827 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49208 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  H01L2924/00014 ,  H01L2224/72

Abstract: Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.

Abstract translation: 从诸如半导体器件的电子部件延伸的弹簧接触元件的临时连接是通过推动电子部件，因此弹簧接触元件的端部垂直地抵靠互连基板的端子，或者通过水平推动互连基板的端子 抵抗弹簧接触元件的端部。 公开了各种终端配置。

公开(公告)号：US20040004216A1

公开(公告)日：2004-01-08

申请号：US10317486

申请日：2002-12-11

Applicant: FormFactor, Inc.

Inventor： Benjamin N. Eldridge ,  Igor Y. Khandros ,  David V. Pedersen ,  Ralph G. Whitten

IPC: H01L023/58

CPC classification number: G01R1/07307 ,  G01R1/07342 ,  G01R1/07371 ,  G01R31/2884 ,  G01R31/2886 ,  H01L22/32 ,  H01L22/34 ,  H01L23/49811 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/13 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/20 ,  H05K3/3421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.

公开(公告)号：US20030107394A1

公开(公告)日：2003-06-12

申请号：US10326423

申请日：2002-12-19

Applicant: FormFactor, Inc.

Inventor： Igor Y. Khandros ,  David V. Pedersen

IPC: G01R031/26

CPC classification number: G01R31/2886 ,  G01R31/287 ,  G01R31/2874 ,  G01R31/318511 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller and promulgating these signals over the relatively many interconnections between the ASICs and the DUTs. The ASICs can also generate at least a portion of these signals in response to control signals from the host controller. Physical alignment techniques are also described. Micromachined indentations on the front surface of the ASICs ensure capturing free ends of the spring contact elements. Micromachined Features on the back surface of the ASICs and the front surface of the interconnection substrate to which they are mounted facilitate precise alignment of a plurality of ASICs on the support substrate.

Abstract translation: 用于执行半导体器件的晶片级老化和测试的技术包括具有有源电子部件的测试基板，例如安装到互连基板或并入其中的ASIC，实现ASIC和多个器件之间的互连的金属弹簧接触元件 在测试晶片（WUT）上的测试（DUT）都被置于真空容器中，使得ASIC可以在与DUT的老化温度无关并且显着低于DUT的老化温度的温度下工作。 弹簧接触元件可以被安装到DUT或ASIC上，并且可以扇出来放松对ASIC和DUT的对准和互连的容限约束。 由于ASIC能够通过相对较少的来自主机控制器的信号线接收用于测试DUT的多个信号，并且在这些信号之间的相对多的互连上发布这些信号，因此实现了互连计数的显着减少和互连基板的随后简化。 ASIC和DUT。 ASIC还可以响应于来自主机控制器的控制信号而产生这些信号的至少一部分。 还描述了物理对准技术。 ASIC的前表面上的微加工凹口确保捕获弹簧接触元件的自由端。 ASIC的后表面上的微加工特征和它们所安装的互连基板的前表面有助于精确地对准支撑基板上的多个ASIC。

公开(公告)号：US20030099737A1

公开(公告)日：2003-05-29

申请号：US09795772

申请日：2001-02-27

Applicant: FormFactor, Inc.

Inventor： Benjamin N. Eldridge ,  Stuart W. Wenzel

IPC: B29C059/02

CPC classification number: G01R3/00 ,  B33Y80/00 ,  B81B2203/0118 ,  B81C1/00611 ,  B81C2201/0108 ,  B81C2201/0125 ,  G01R1/0483 ,  G01R1/06711 ,  G01R1/06716 ,  G01R1/06727 ,  G01R1/06733 ,  G01R1/07342 ,  H01L23/4822 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01R12/52 ,  H01R13/24 ,  H01R13/2407 ,  H05K3/4092 ,  H05K7/1069 ,  H01L2924/00

Abstract: A forming tool with one or more embossing tooth, and preferably, a plurality of such embossing teeth, arranged on a substantially planar substrate, is disclosed. Each embossing tooth is configured for forming a sacrificial layer to provide a contoured surface for forming a microelectronic spring structure. Each embossing tooth has a protruding area corresponding to a base of a microelectronic spring, and a sloped portion corresponding to a beam contour of a microelectronic spring. Numerous methods for making a forming tool are also disclosed. The methods include a material removal method, a molding method, a repetitive-stamping method, tang-bending methods, and segment-assembly methods.

Abstract translation: 公开了一种具有一个或多个压花齿的成形工具，优选地，布置在基本平坦的基底上的多个这样的压花齿。 每个压花齿构造成用于形成牺牲层以提供用于形成微电子弹簧结构的轮廓表面。 每个压花齿具有对应于微电子弹簧的基部的突出区域和对应于微电子弹簧的光束轮廓的倾斜部分。 还公开了用于制造成形工具的许多方法。 这些方法包括材料去除方法，成型方法，重复冲压方法，弯曲方法和段组装方法。