公开(公告)号：US20070023906A1

公开(公告)日：2007-02-01

申请号：US11543084

申请日：2006-10-05

申请人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

发明人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/28 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00

摘要： A semiconductor device-composing substrate 10 has a support base 12, an interconnect layer 14 including interconnects 13, and an insulating resin layer 16. The semiconductor device-composing substrate 10 also has a mounting region D1 on which a semiconductor chip 30 is to be mounted. The insulating resin layer 16 is formed on the interconnect layer 14. Chip-connecting electrodes 17, external electrode pads 18 and the resin stopper patterns 19 are formed in the insulating resin layer 16. The chip-connecting electrodes 17 are provided in the mounting region D1. The external electrode pads 18 are provided outside the mounting region D1. The resin stopper patterns 19 are provided between the mounting region D1 and the external electrode pads 18.

摘要翻译： 半导体器件组成基板10具有支撑基底12，包括互连13的互连层14和绝缘树脂层16。 半导体器件组合基板10还具有安装半导体芯片30的安装区域D1。 绝缘树脂层16形成在互连层14上。 芯片连接电极17，外部电极焊盘18和树脂阻挡图案19形成在绝缘树脂层16中。 芯片连接电极17设置在安装区域D1中。 外部电极焊盘18设置在安装区域D1的外侧。 树脂止挡图案19设置在安装区域D 1和外部电极焊盘18之间。

公开(公告)号：US20070020804A1

公开(公告)日：2007-01-25

申请号：US11528422

申请日：2006-09-28

申请人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

发明人： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/28 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/81054 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00012

摘要： The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting the solder electrode 22 and connecting it to the electrode pad 16, thus connecting the interconnect substrate 10 and the electronic circuit chip 20. A first metal material, exposed in the surface of the electrode pad 16 opposite to an insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material exposed in the surface of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.

摘要翻译： 根据本发明的实施例的制造电子电路器件的方法包括制备包括互连14的互连衬底10和与互连14一体形成的电极焊盘16; 制备包括焊料电极22的电子电路芯片20; 并且熔化焊料电极22并将其连接到电极焊盘16，从而连接互连基板10和电子电路芯片20。 暴露在与绝缘树脂层12相对并构成电极焊盘16的电极焊盘16的表面中的第一金属材料与相互连接的互连14的表面中露出的第二金属材料相比，形成比形成氧化物的更高的自由能 到绝缘树脂层12并构成互连14。

公开(公告)号：US06822336B2

公开(公告)日：2004-11-23

申请号：US10180602

申请日：2002-06-26

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/563 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81355 ,  H01L2224/81395 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device according to the invention is provided with an electrode used for connecting a semiconductor chip and a wiring board or plural semiconductor chips, an additive layer formed by doping an additive including at least one type of atom different from an atom forming the electrode in the vicinity of the surface of the electrode and an insulator formed on the surface of the electrode.

摘要翻译： 根据本发明的半导体器件设置有用于连接半导体芯片和布线板或多个半导体芯片的电极，通过掺杂包含至少一种不同于形成电极的原子的原子的添加剂形成的添加层 电极表面附近和形成在电极表面上的绝缘体。

公开(公告)号：US08456020B2

公开(公告)日：2013-06-04

申请号：US12906377

申请日：2010-10-18

申请人： Yoichiro Kurita ,  Masaya Kawano

发明人： Yoichiro Kurita ,  Masaya Kawano

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/60 ,  H01L24/24 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.

摘要翻译： 半导体封装具有：第一芯片; 和第二芯片。 第一芯片具有：形成在第一芯片的主表面上的绝缘树脂层; 在所述绝缘树脂层的区域中形成为贯通所述绝缘树脂层并电连接到所述第二芯片的凸点状的第一内部电极组， 用于与外部设备电连接的外部电极组; 和与外部电极组电连接的静电放电保护元件组。 第一内部电极组不与静电放电保护元件组电连接。

公开(公告)号：US08058165B2

公开(公告)日：2011-11-15

申请号：US12853660

申请日：2010-08-10

申请人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H05K3/423 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/113 ,  H05K1/114 ,  H05K3/025 ,  H05K3/064 ,  H05K2203/016 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

摘要翻译： 根据本发明的实施例的制造方法包括在支撑衬底70上形成种子金属层20a，在种子金属层20a上形成包括互连18的互连层10，在形成互连之后移除支撑衬底70 层10，并且图案化种子金属层20a，从而在移除支撑衬底之后形成互连20。

公开(公告)号：US07977158B2

公开(公告)日：2011-07-12

申请号：US12805048

申请日：2010-07-08

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L21/60 ,  H01L21/603

CPC分类号： B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part.

摘要翻译： 接合形成在第一电子部件上的第一金属接合部和形成在第二电子部件上的第二金属接合部的电子设备的制造方法包括：将第一金属接合部直接放置在第二金属接合部上的第一工序， 向所述第一电子部件和所述第二电子部件施加压力，将所述第一金属接合部与所述第二金属接合部以固相扩散接合，释放所施加的压力，以及第二加工所述第一电子部件和所述第二电子部件 电子部件在预定温度下使得第一金属接合部分和第二金属接合部分通过熔化第一金属接合部分和第二金属接合部分而接合在一起。

公开(公告)号：US20110104887A1

公开(公告)日：2011-05-05

申请号：US12926642

申请日：2010-12-01

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L21/283

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105

摘要： A method of manufacturing a semiconductor element including a semiconductor substrate, a conductive post portion provided on the semiconductor substrate to protrude therefrom, and a solder layer provided on the conductive post portion, includes forming on the semiconductor substrate the conductive post portion having a distal end surface curved in a substantially arc shape by electrolytic plating, forming an intermediate solder layer on the distal end surface of the conductive post portion, and reflowing the intermediate solder layer to form the solder layer which has a thickest portion at a top of the distal end surface of the conductive post portion.

摘要翻译： 一种制造半导体元件的方法，包括半导体衬底，设置在半导体衬底上以从其突出的导电柱部分和设置在导电柱部分上的焊料层，包括在半导体衬底上形成具有远端的导电柱部分 表面通过电解电镀弯曲成大致圆弧形状，在导电柱部分的远端表面上形成中间焊料层，并回流中间焊料层以形成在远端顶部具有最厚部分的焊料层 导电柱部分的表面。

公开(公告)号：US07931411B2

公开(公告)日：2011-04-26

申请号：US12461725

申请日：2009-08-21

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： G02B6/36

CPC分类号： G02B6/4201 ,  G02B6/4214 ,  G02B6/4232 ,  G02B6/4239 ,  G02B6/4246 ,  G02B6/43

摘要： An optical transmission apparatus includes a wiring board, an electronic device mounted on the wiring board, a connection part that mechanically connects the electronic device and the wiring board to each other in such a manner that the electronic device and the wiring board face each other at a certain distance and electrically connects the electronic device and the wiring board to each other, an optical cable connector that is in contact with the electronic device, and an optical cable connected to the optical cable connector. The optical cable connector has a part that is inserted between the electronic device and the wiring board. A signal is transmitted between the part and the electronic device.

摘要翻译： 光传输装置包括布线板，安装在布线板上的电子装置，将电子装置和布线基板彼此机械连接的连接部，使电子装置和布线基板彼此面对 电子设备和布线板彼此电连接，与电子设备接触的光缆连接器和连接到光缆连接器的光缆。 光缆连接器具有插入在电子设备和布线板之间的部分。 信号在部件和电子设备之间传输。

公开(公告)号：US07812446B2

公开(公告)日：2010-10-12

申请号：US12107795

申请日：2008-04-23

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L23/34

CPC分类号： G11C5/063 ,  G11C5/02 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/0401

摘要： A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

摘要翻译： 描述了制造包括PMOS晶体管和NMOS晶体管的半导体器件的方法。 该方法有助于分别获得用于NMOS晶体管和PMOS晶体管的合适组合物的FUSI相，具有较少的掩模层和通过较少数量的制造步骤。

公开(公告)号：US07800233B2

公开(公告)日：2010-09-21

申请号：US11491180

申请日：2006-07-24

申请人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Koji Soejima ,  Yoichiro Kurita

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/423 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/113 ,  H05K1/114 ,  H05K3/025 ,  H05K3/064 ,  H05K2203/016 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

摘要翻译： 根据本发明的实施例的制造方法包括在支撑衬底70上形成种子金属层20a，在种子金属层20a上形成包括互连18的互连层10，在形成互连之后移除支撑衬底70 层10，并且图案化种子金属层20a，从而在去除支撑衬底之后形成互连20。