公开(公告)号：US6066577A

公开(公告)日：2000-05-23

申请号：US937367

申请日：1997-09-25

申请人： Edward C. Cooney, III ,  Hyun K. Lee ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Edward C. Cooney, III ,  Hyun K. Lee ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28568 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76838 ,  Y10S438/963

摘要： Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-free silicon dioxide barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.

摘要翻译： 通过在绝缘体材料和金属之间形成无氟二氧化硅阻挡层来提高金属抵抗从暴露于氟的氟降低的方法。 本发明特别可用于改善半导体结构中的冶金冶金等的耐腐蚀和耐中毒性。 本发明还涉及通过该方法制成的集成电路结构。

公开(公告)号：US09831122B2

公开(公告)日：2017-11-28

申请号：US13482864

申请日：2012-05-29

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/5226 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

公开(公告)号：US20130320536A1

公开(公告)日：2013-12-05

申请号：US13482864

申请日：2012-05-29

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Robert K. Leidy

IPC分类号： H01L23/52 ,  G06F17/50 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

摘要翻译： 集成电路（IC），设计结构及其制作方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的电介质层; 设置在电介质层上的一组电线组件，该组电线组件包括靠近第二电线组件设置的第一电线组件; 设置在所述第一线材部件上的接合焊盘，所述接合焊盘包括暴露部分; 围绕所述接合焊盘和所述一组导线部件的一部分设置在所述电介质层上的钝化层，所述钝化层通过连接到所述第二导线部件限定线结构; 以及布线在靠近接合焊盘的钝化层上并通过导线结构通孔连接到第二导线部件的线结构。

公开(公告)号：US08575022B2

公开(公告)日：2013-11-05

申请号：US13304772

申请日：2011-11-28

申请人： Gregory S. Chrisman ,  Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Thomas L. McDevitt ,  Eva A. Shah

发明人： Gregory S. Chrisman ,  Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Thomas L. McDevitt ,  Eva A. Shah

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L23/562 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5227 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.

摘要翻译： 一种用于制造提供在上表面具有第一高度的金属线的结构的结构和方法。 围绕所述金属线的绝缘材料被蚀刻到所述上表面的所述第一高度以下的第二高度。 在蚀刻所述绝缘材料之后，来自所述上表面的金属线被平坦化以从所述金属线的横向边缘部分去除足够的材料，使得所述侧边缘部分的高度等于围绕所述绝缘材料的所述绝缘材料的所述第二高度 金属丝。

公开(公告)号：US08564113B2

公开(公告)日：2013-10-22

申请号：US13444193

申请日：2012-04-11

申请人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC分类号： H01L23/488

CPC分类号： H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US20130175073A1

公开(公告)日：2013-07-11

申请号：US13345120

申请日：2012-01-06

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee ,  Xiao H. Liu

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee ,  Xiao H. Liu

IPC分类号： H05K1/02 ,  H05K1/09 ,  B05D5/12

CPC分类号： H01L23/5227 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。 在第一线退火之后，形成与第一线垂直对准的第二线。 形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。

公开(公告)号：US20130105981A1

公开(公告)日：2013-05-02

申请号：US13285443

申请日：2011-10-31

申请人： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

摘要： Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

摘要翻译： 用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。 使用器件基板的第一表面形成产品芯片的器件结构。 在产品芯片上形成用于器件结构的互连结构的布线层。 布线层被平坦化。 临时处理晶片可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。 然后将临时手柄晶片从组件中取出。

公开(公告)号：US08242591B2

公开(公告)日：2012-08-14

申请号：US12540510

申请日：2009-08-13

申请人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC分类号： H01L23/488

CPC分类号： H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

摘要： A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

摘要翻译： 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US07972965B2

公开(公告)日：2011-07-05

申请号：US11862706

申请日：2007-09-27

申请人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M. Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

发明人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M. Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

IPC分类号： H01L21/311

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

公开(公告)号：US20100263998A1

公开(公告)日：2010-10-21

申请号：US12426561

申请日：2009-04-20

申请人： Felix P. Anderson ,  Edward C. Cooney, III ,  Thomas L. Mcdevitt ,  Anthony K. Stamper

发明人： Felix P. Anderson ,  Edward C. Cooney, III ,  Thomas L. Mcdevitt ,  Anthony K. Stamper

IPC分类号： H01H59/00 ,  H01L21/50 ,  G06F17/50 ,  H01L21/3213

CPC分类号： H01H59/0009 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.

摘要翻译： 本文提供垂直集成MEMS开关，制造这种垂直开关的设计结构和方法。 制造MEMS开关的方法包括在晶片中形成至少两个垂直延伸的通孔，并用金属填充至少两个垂直延伸的通孔以形成至少两个垂直延伸的导线。 该方法还包括从底侧打开晶片中的空隙，使得垂直延伸的线中的至少一个可在空隙内移动。