公开(公告)号：US10079228B1

公开(公告)日：2018-09-18

申请号：US15463795

申请日：2017-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/45

Abstract: An electric static discharge (ESD) diode pair is disclosed. The first diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a first conductivity and a second diode junction portion of a second conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. The second diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a second conductivity and a second diode junction portion having a first conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. A common electrical contact is in direct contact first diode junction portion for each of the first diode and the second diode.

公开(公告)号：US20180247873A1

公开(公告)日：2018-08-30

申请号：US15967845

申请日：2018-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/033 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L21/768 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

公开(公告)号：US10056379B1

公开(公告)日：2018-08-21

申请号：US15662874

申请日：2017-07-28

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L29/808 ,  H01L27/092 ,  H01L27/112 ,  H01L27/06 ,  H01L27/098 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/0922 ,  H01L27/0629 ,  H01L27/085 ,  H01L27/098 ,  H01L27/11273 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/0891 ,  H01L29/1066 ,  H01L29/42392 ,  H01L29/66909 ,  H01L29/78642 ,  H01L29/8083

Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

公开(公告)号：US20180233503A1

公开(公告)日：2018-08-16

申请号：US15825088

申请日：2017-11-28

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L27/082 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823885 ,  H01L21/845 ,  H01L23/528 ,  H01L27/082 ,  H01L27/0924 ,  H01L27/11273 ,  H01L29/0649 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66795 ,  H01L29/7788 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/783 ,  H01L29/785 ,  H01L29/7853

Abstract: CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.

公开(公告)号：US20180233501A1

公开(公告)日：2018-08-16

申请号：US15434753

申请日：2017-02-16

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762

Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.

公开(公告)号：US09997472B2

公开(公告)日：2018-06-12

申请号：US15401539

申请日：2017-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/66 ,  H01L23/00 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  B82Y10/00

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US09991359B1

公开(公告)日：2018-06-05

申请号：US15623774

申请日：2017-06-15

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/423

CPC classification number: H01L29/66356 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7391

Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

公开(公告)号：US09972684B2

公开(公告)日：2018-05-15

申请号：US15453118

申请日：2017-03-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Nicolas J. Loubet ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/1079 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02483 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/0262 ,  H01L29/0684 ,  H01L29/16 ,  H01L29/7849

Abstract: A method for forming a compressively strained semiconductor substrate includes forming a lattice adjustment layer on a semiconductor substrate by forming compound clusters within an epitaxially grown semiconductor matrix. The lattice adjustment layer includes a different lattice constant than the semiconductor substrate. A rare earth oxide is grown and lattice matched to the lattice adjustment layer. A semiconductor layer is grown and lattice matched to the rare earth oxide and includes a same material as the semiconductor substrate such that the semiconductor layer is compressively strained.

公开(公告)号：US20180095053A1

公开(公告)日：2018-04-05

申请号：US15615414

申请日：2017-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ali Afzali-Ardakani ,  Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: G01N27/414 ,  G01N27/30 ,  H01L29/16 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417

CPC classification number: G01N27/4145 ,  G01N27/30 ,  G01N27/3278 ,  H01L29/0684 ,  H01L29/16 ,  H01L29/20 ,  H01L29/417

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.

公开(公告)号：US09917179B2

公开(公告)日：2018-03-13

申请号：US15220723

申请日：2016-07-27

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/6681 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a semiconductor device comprises depositing alternating layers of a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate in a stacked configuration, forming one or more first openings in the stacked configuration to a depth penetrating below an upper surface of a bottom second dielectric layer of the plurality of second dielectric layers, forming one or more second openings in the stacked configuration to a depth corresponding to an upper surface of the substrate or below an upper surface of the substrate, removing the plurality of second dielectric layers from the stacked configuration to form a plurality of gaps, and epitaxially growing a semiconductor material from a seed layer in the one or more second openings to fill the one or more first and second openings and the plurality of gaps, wherein defects caused by a lattice mismatch between the epitaxially grown semiconductor material and a material of the substrate are contained at a bottom portion of the one or more second openings.