公开(公告)号：US07880295B2

公开(公告)日：2011-02-01

申请号：US12618399

申请日：2009-11-13

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H01L23/12

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

摘要翻译： 一种布线板，包括：第一表面，其上设置有第一电极;第二表面，其上设置有第二电极; 至少单个绝缘层和至少一个布线层; 以及一个或多个安装的半导体元件，其中设置在第二表面上的第二电极嵌入在绝缘层中，在第二电极的第二表面侧上的暴露表面的相对侧上的表面连接到布线 层，并且第二电极的全部或部分侧面不与绝缘层接触。

公开(公告)号：US08552570B2

公开(公告)日：2013-10-08

申请号：US12811733

申请日：2009-01-06

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

IPC分类号： H01L29/40

CPC分类号： H05K3/4647 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

摘要翻译： 在布线板中，绝缘层和布线层交替层叠，并且布线层通过通孔电连接。 布线基板包括布置在第一表面中并嵌入绝缘层中的第一端子，布置在与第一表面相对的第二表面中并嵌入绝缘层中的第二端子，以及布置在绝缘层中并与第一端子接触的焊盘 终端。 通孔将焊盘和与绝缘层交替层压的布线层电连接。 在接地侧的每个通孔的端部没有形成连接接口，但是在布线层侧的每个通孔的端部形成有连接接口。

公开(公告)号：US20100295191A1

公开(公告)日：2010-11-25

申请号：US12811733

申请日：2009-01-06

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima ,  Yoichiro Kurita

IPC分类号： H01L23/49 ,  H01L21/60 ,  H05K1/11 ,  H01R43/00

CPC分类号： H05K3/4647 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

摘要翻译： 在布线板中，绝缘层和布线层交替层叠，并且布线层通过通孔电连接。 布线基板包括布置在第一表面中并嵌入绝缘层中的第一端子，布置在与第一表面相对的第二表面中并嵌入绝缘层中的第二端子，以及布置在绝缘层中并与第一端子接触的焊盘 终端。 通孔将焊盘和与绝缘层交替层压的布线层电连接。 在接地侧的每个通孔的端部没有形成连接接口，但是在布线层侧的每个通孔的端部形成有连接接口。

公开(公告)号：US07262486B2

公开(公告)日：2007-08-28

申请号：US11154514

申请日：2005-06-17

申请人： Masaya Kawano ,  Tsutomu Tashiro ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Tsutomu Tashiro ,  Yoichiro Kurita

IPC分类号： H01L21/40

CPC分类号： H01L21/76286 ,  H01L21/84

摘要： The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device formation region A1 of the SOI substrate 1. The through electrode 40 reaches the insulating layer 20 from the silicon layer 30. Specifically, the through electrode 40 extends to an inner part of the insulating layer 20 originating from a surface of the silicon layer 30 while penetrating the silicon layer 30. Here, an end face 40a of the through electrode 40 at the insulating layer 20 side stops inside the insulating layer 20.

摘要翻译： SOI衬底1具有支撑衬底10，形成在支撑衬底10上的绝缘层20和形成在绝缘层20上的硅层30。 在SOI衬底1的器件形成区域A 1中设置有贯通电极40。 通孔40从硅层30到达绝缘层20。 具体地，贯穿电极40延伸到绝缘层20的内部，源于硅层30的表面，同时穿透硅层30。 这里，绝缘层20侧的贯通电极40的端面40a停止在绝缘层20的内部。

公开(公告)号：US08456020B2

公开(公告)日：2013-06-04

申请号：US12906377

申请日：2010-10-18

申请人： Yoichiro Kurita ,  Masaya Kawano

发明人： Yoichiro Kurita ,  Masaya Kawano

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/60 ,  H01L24/24 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.

摘要翻译： 半导体封装具有：第一芯片; 和第二芯片。 第一芯片具有：形成在第一芯片的主表面上的绝缘树脂层; 在所述绝缘树脂层的区域中形成为贯通所述绝缘树脂层并电连接到所述第二芯片的凸点状的第一内部电极组， 用于与外部设备电连接的外部电极组; 和与外部电极组电连接的静电放电保护元件组。 第一内部电极组不与静电放电保护元件组电连接。

公开(公告)号：US07598590B2

公开(公告)日：2009-10-06

申请号：US11143672

申请日：2005-06-03

申请人： Masaya Kawano ,  Tsutomu Tashiro ,  Yoichiro Kurita

发明人： Masaya Kawano ,  Tsutomu Tashiro ,  Yoichiro Kurita

IPC分类号： H01L29/66

CPC分类号： H01L23/585 ,  H01L21/76264 ,  H01L23/562 ,  H01L23/564 ,  H01L2224/32145

摘要： The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed on the insulating layer 14 with the layered structure. The semiconductor substrate 10 has a circuit forming region A1 provided in the silicon layer 16. An insulating region 18 is provided on the semiconductor substrate 10. The insulating region 18 is provided so as to surround the entire side face of the circuit forming region A1.

摘要翻译： 半导体芯片1具有半导体基板10.在本实施方式中，作为SOI基板的半导体基板10由支撑基板12，形成在支撑基板12上的层叠结构的绝缘层14构成， 以及形成在具有层状结构的绝缘层14上的硅层16。 半导体衬底10具有设置在硅层16中的电路形成区域A.绝缘区域18设置在半导体衬底10上。绝缘区域18设置成围绕电路形成区域A1的整个侧面。

公开(公告)号：US08349649B2

公开(公告)日：2013-01-08

申请号：US12905167

申请日：2010-10-15

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L23/02 ,  H01L21/40 ,  H01L21/48 ,  H01L21/52

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00

摘要： A semiconductor device includes a first interposer provided with a first chip first interconnection; a first chip arranged to contact the first interposer in one surface of the first chip; a second interposer arranged to contact the other surface of the first chip and provided with a first chip second interconnection; and a second chip group mounted on the second interposer. The first chip has a circuit forming surface on which a circuit element is formed, as one of the surfaces of the first chip, and the first chip first interconnection and the first chip second interconnection are electrically connected with the circuit element. A through electrode is formed to pass from the one of the surfaces of the first chip to the other surface, and one of the first chip first interconnection and the first chip second interconnection is electrically connected with the circuit element through the through electrode.

摘要翻译： 半导体器件包括具有第一芯片第一互连的第一插入器; 布置成在所述第一芯片的一个表面中接触所述第一插入件的第一芯片; 第二插入器，布置成接触第一芯片的另一表面并且设置有第一芯片第二互连; 以及安装在第二插入器上的第二芯片组。 第一芯片具有形成电路元件的电路形成表面，作为第一芯片的一个表面，并且第一芯片第一互连和第一芯片第二互连电路与电路元件电连接。 通孔形成为从第一芯片的一个表面到另一个表面，并且第一芯片第一互连和第一芯片第二互连中的一个通过贯通电极与电路元件电连接。

公开(公告)号：US08278143B2

公开(公告)日：2012-10-02

申请号：US13067723

申请日：2011-06-22

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L21/60 ,  H01L21/603

CPC分类号： B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.

摘要翻译： 接合形成在第一电子部件上的第一金属接合部和形成在第二电子部件上的第二金属接合部的电子设备的制造方法包括：将第一金属接合部直接放置在第二金属接合部上的第一工序， 向所述第一电子部件和所述第二电子部件施加压力，将所述第一金属接合部与所述第二金属接合部以固相扩散接合，释放所施加的压力，以及第二加工所述第一电子部件和所述第二电子部件 电子部件在预定温度下通过熔化第一金属接合部和第二金属接合部中的至少一个而使第一金属接合部和第二金属接合部接合在一起。

公开(公告)号：US20110253767A1

公开(公告)日：2011-10-20

申请号：US13067723

申请日：2011-06-22

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L21/02 ,  B23K31/02

CPC分类号： B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.

摘要翻译： 接合形成在第一电子部件上的第一金属接合部和形成在第二电子部件上的第二金属接合部的电子设备的制造方法包括：将第一金属接合部直接放置在第二金属接合部上的第一工序， 向所述第一电子部件和所述第二电子部件施加压力，将所述第一金属接合部与所述第二金属接合部以固相扩散接合，释放所施加的压力，以及第二加工所述第一电子部件和所述第二电子部件 电子部件在预定温度下通过熔化第一金属接合部和第二金属接合部中的至少一个而使第一金属接合部和第二金属接合部接合在一起。

公开(公告)号：US07556983B2

公开(公告)日：2009-07-07

申请号：US11345780

申请日：2006-02-02

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L21/44

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

摘要： A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.