公开(公告)号：US20130292838A1

公开(公告)日：2013-11-07

申请号：US13939146

申请日：2013-07-10

申请人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

发明人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

IPC分类号： H01L23/488 ,  H01L21/50

CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

摘要翻译： 本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。 本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘 包。

公开(公告)号：US08535989B2

公开(公告)日：2013-09-17

申请号：US12753637

申请日：2010-04-02

申请人： Robert L. Sankman ,  John S. Guzek

发明人： Robert L. Sankman ,  John S. Guzek

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

公开(公告)号：US08513792B2

公开(公告)日：2013-08-20

申请号：US12384984

申请日：2009-04-10

申请人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

发明人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

摘要翻译： 本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。 本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘 包。

公开(公告)号：US08313958B2

公开(公告)日：2012-11-20

申请号：US12778335

申请日：2010-05-12

申请人： Rajasekaran Swaminathan ,  Ravindranath Mahajan ,  John S. Guzek

发明人： Rajasekaran Swaminathan ,  Ravindranath Mahajan ,  John S. Guzek

IPC分类号： H01L21/50

CPC分类号： H01L24/11 ,  H01L21/563 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/81121 ,  H01L2224/81122 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81457 ,  H01L2224/8146 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/95133 ,  H01L2224/95136 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/81805

摘要： The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged.

摘要翻译： 本公开涉及制造微电子封装的领域，其中微电子封装的微电子器件可具有包括形成在附接结构上的磁性材料的磁性附着结构。 微电子器件可以在具有磁场的衬底上对准，然后在附着于衬底的同时保持在其上。 微电子器件还可以与对准板对齐，该对准板在包装时磁性对准并保持组件就位。

公开(公告)号：US20110318850A1

公开(公告)日：2011-12-29

申请号：US13225745

申请日：2011-09-06

申请人： John S. Guzek ,  Mahadevan Suryakumar ,  Hamid R. Azimi

发明人： John S. Guzek ,  Mahadevan Suryakumar ,  Hamid R. Azimi

IPC分类号： H01L21/66

CPC分类号： H01L23/49833 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

摘要翻译： 微电子封装包括具有第一表面区域（125）的第一衬底（120）和具有第二表面区域（135）的第二衬底（130）。 第一衬底包括在第一表面处具有第一间距（127）的第一组互连（126）和在第二表面（222）处具有第二间距（129）的第二组互连（128）。 第二衬底使用第二组互连件耦合到第一衬底，并且包括具有第三间距（237）和第三组互连（236）的第三组互连（236），并且内部导电层（233,234）以微孔（ 240）。 第一间距小于第二间距，第二间距小于第三间距，第一表面积小于第二表面积。

公开(公告)号：US20110281375A1

公开(公告)日：2011-11-17

申请号：US12778335

申请日：2010-05-12

申请人： Rajasekaran Swaminathan ,  Ravindranath Ravi Mahajan ,  John S. Guzek

发明人： Rajasekaran Swaminathan ,  Ravindranath Ravi Mahajan ,  John S. Guzek

IPC分类号： H01L21/50

CPC分类号： H01L24/11 ,  H01L21/563 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/95 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/81121 ,  H01L2224/81122 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81411 ,  H01L2224/81457 ,  H01L2224/8146 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/95133 ,  H01L2224/95136 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/81805

摘要： The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged.

摘要翻译： 本公开涉及制造微电子封装的领域，其中微电子封装的微电子器件可具有包括形成在附接结构上的磁性材料的磁性附着结构。 微电子器件可以在具有磁场的衬底上对准，然后在附着于衬底的同时保持在其上。 微电子器件还可与对准板对齐，该对准板在包装时磁性对准和保持部件就位。

公开(公告)号：US20110241215A1

公开(公告)日：2011-10-06

申请号：US12753637

申请日：2010-04-02

申请人： Robert L. Sankman ,  John S. Guzek

发明人： Robert L. Sankman ,  John S. Guzek

IPC分类号： H01L23/522 ,  H01L21/60 ,  H01L21/78 ,  H01L23/485

CPC分类号： H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

摘要翻译： 重构的晶片包括具有平坦表面的刚性块和平行于平坦表面设置的基底表面。 多个骰子嵌入刚体中。 多个骰子包括通过与平坦表面共面露出的端子。 形成重构的晶片的过程包括去除刚性质量块中的一些以露出端子，同时将多个裸片保持在刚性质量块中。 形成设备的过程包括将一个设备与重构的晶片分开。

公开(公告)号：US20100207265A1

公开(公告)日：2010-08-19

申请号：US12378953

申请日：2009-02-19

申请人： Sriram Muthukumar ,  Nicholas R. Watts ,  John S. Guzek

发明人： Sriram Muthukumar ,  Nicholas R. Watts ,  John S. Guzek

IPC分类号： H01L23/00 ,  H01L21/02

CPC分类号： H01L23/49822 ,  H01L2224/0554 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0271 ,  H05K3/28 ,  H05K3/4682 ,  H05K2203/0582 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.

摘要翻译： 本发明的实施例涉及一种加强半导体无芯封装基板以提高刚性和抗翘曲性的方法。 该方法的一个实施例包括在无芯封装基板的第二级互连（封装 - 板间互连）侧上的多个接触焊盘上设置牺牲掩模，在牺牲掩模周围形成模制的加强件，而不增加有效厚度 并且去除牺牲掩模以在对应于接触焊盘的模制加强件中形成多个空腔。 实施例还包括用导电材料电镀接触垫的表面和模制空腔中的空腔的侧壁。

公开(公告)号：US07042077B2

公开(公告)日：2006-05-09

申请号：US10825400

申请日：2004-04-15

申请人： Michael J. Walk ,  Hamid Azimi ,  John S. Guzek ,  Charan K. Gurumurthy

发明人： Michael J. Walk ,  Hamid Azimi ,  John S. Guzek ,  Charan K. Gurumurthy

IPC分类号： H01L23/02

CPC分类号： H05K1/0271 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15312 ,  H01L2924/15313 ,  H05K1/162 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/09481 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734

摘要： A system may include a coreless substrate, a layer of material attached to the substrate, the layer of material having a lower elastic modulus than the substrate, an interposer coupled to the layer of material, and a capacitive layer coupled to the interposer.

摘要翻译： 系统可以包括无芯衬底，附着到衬底的材料层，具有比衬底更低的弹性模量的材料层，耦合到材料层的插入器以及耦合到插入器的电容层。

公开(公告)号：US09999129B2

公开(公告)日：2018-06-12

申请号：US12590650

申请日：2009-11-12

申请人： John S. Guzek ,  Mihir K. Roy ,  Brent M. Roberts

发明人： John S. Guzek ,  Mihir K. Roy ,  Brent M. Roberts

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/64 ,  H05K1/16 ,  H01L23/00 ,  H05K1/02 ,  H05K1/11

CPC分类号： H05K1/165 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0254 ,  H05K1/0262 ,  H05K1/116 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1572 ,  H01L2924/00

摘要： A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).