公开(公告)号：US5993686A

公开(公告)日：1999-11-30

申请号：US659419

申请日：1996-06-06

申请人： Christopher C. Streinz ,  Brian L. Mueller ,  Michael A. Lucarelli ,  Max H. Walters

发明人： Christopher C. Streinz ,  Brian L. Mueller ,  Michael A. Lucarelli ,  Max H. Walters

IPC分类号： C09G1/02 ,  C09K3/14 ,  C09K13/04 ,  H01L21/304 ,  H01L21/321 ,  H01L21/3213 ,  C09K13/00 ,  C23F3/00 ,  H01L21/306

CPC分类号： C09G1/02 ,  H01L21/3213

摘要： A chemical mechanical polishing slurry comprising an oxidizing agent, a fluoride containing additive and an abrasive and a method for using the fluoride containing additive chemical mechanical polishing slurry to remove tungsten and titanium from substrates.

摘要翻译： 包含氧化剂，含氟化物添加剂和研磨剂的化学机械抛光浆料以及使用含氟化物添加剂化学机械抛光浆料从基材除去钨和钛的方法。

公开(公告)号：US5942449A

公开(公告)日：1999-08-24

申请号：US704328

申请日：1996-08-28

申请人： Scott G. Meikle

发明人： Scott G. Meikle

IPC分类号： H01L21/321 ,  H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/321 ,  H01L21/3213 ,  H01L21/32134

摘要： A method for removing a portion of an upper layer of one material from an underlying layer of another material to form a uniformly planar surface on a semiconductor wafer. In accordance with one embodiment of the invention, an upper section of the upper layer is etched to an intermediate point in the upper layer. The etching step removes the upper section of the upper layer and leaves only a lower section of the upper layer on the wafer. The lower section of the upper layer is then planarized to a final endpoint. The etching step preferably moves the majority of the upper layer from the wafer so that the remaining portion of the upper layer is thick enough to allow the planarization step to produce a uniformly planar finished surface on the wafer.

公开(公告)号：US5834125A

公开(公告)日：1998-11-10

申请号：US78929

申请日：1993-06-16

申请人： Chuen-Der Lien

发明人： Chuen-Der Lien

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  B32B17/00

CPC分类号： G03F7/091 ,  H01L21/0276 ,  H01L21/3213 ,  G03F7/09 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/31667

摘要： An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and preferably does not react with either the reflective layer or the anti-reflective layer. In particular embodiments, the barrier layer is a thin layer of silicon dioxide SiO.sub.2 or silicon nitride Si.sub.3 N.sub.4, and the anti-reflective layer is titanium-tungsten TiW, titanium nitride TiN, or amorphous silicon.

摘要翻译： 提供了具有阻挡层和抗反射层的抗反射涂层。 阻挡层停止抗反射层与下层或基底之间的反应，不使防反射层反射，并且优选不与反射层或抗反射层反应。 在具体实施方案中，阻挡层是二氧化硅SiO 2或氮化硅Si 3 N 4的薄层，抗反射层是钛 - 钨TiW，氮化钛TiN或非晶硅。

公开(公告)号：US5767013A

公开(公告)日：1998-06-16

申请号：US778678

申请日：1997-01-03

申请人： Nae Hak Park ,  Chang Soo Kim ,  Yun Hee Kim

发明人： Nae Hak Park ,  Chang Soo Kim ,  Yun Hee Kim

IPC分类号： H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/3213 ,  H01L21/76838

摘要： A method for forming an interconnection pattern in a semiconductor device for reducing metallic reflection, includes the steps of forming a conductive layer on a substrate, polishing the conductive layer to form a rugged surface on the conductive layer, and selectively removing the polished conductive layer to form the interconnection pattern.

摘要翻译： 一种用于在用于减少金属反射的半导体器件中形成布线图案的方法，包括以下步骤：在基板上形成导电层，研磨导电层以在导电层上形成粗糙表面，并且将抛光的导电层选择性地去除 形成互连图案。

公开(公告)号：US5585016A

公开(公告)日：1996-12-17

申请号：US94676

申请日：1993-07-20

申请人： Ciaran Hanrahan ,  Andrew P. Stack

发明人： Ciaran Hanrahan ,  Andrew P. Stack

IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/3213 ,  B23K26/00 ,  H01G7/00

CPC分类号： H01L28/10 ,  H01L21/3105 ,  H01L21/3213 ,  Y10T29/435

摘要： A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patterning an area of the conductive thin film. Laser patterning is performed by applying the laser along the outer boundary of the area to be patterned to energetically remove the conductive thin film along this boundary.

摘要翻译： 用于测试制造线中的污染物的半导体电容器是通过在半导体衬底上形成绝缘材料层，在绝缘材料层上形成导电薄膜层，以及激光构图导电薄膜 电影。 通过沿着要构图的区域的外边界应用激光来沿着该边界能量地去除导电薄膜来进行激光图案化。

公开(公告)号：US20190187562A1

公开(公告)日：2019-06-20

申请号：US16209871

申请日：2018-12-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Harn-Jiunn Wang ,  Kai-Ming Liu ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/3213

CPC分类号： G03F7/2022 ,  H01L21/027 ,  H01L21/3213

摘要： A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.

公开(公告)号：US20180197915A1

公开(公告)日：2018-07-12

申请号：US15824448

申请日：2017-11-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Benjamin D. Briggs ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L27/112 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/8229 ,  H01L21/67 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/306 ,  H01L21/04 ,  H01L43/10 ,  H01L27/105

CPC分类号： H01L27/222 ,  H01L21/02019 ,  H01L21/0475 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67063 ,  H01L21/8229 ,  H01L21/8239 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/11502 ,  H01L27/11585 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2924/1441

摘要： A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

公开(公告)号：US09916984B2

公开(公告)日：2018-03-13

申请号：US15483273

申请日：2017-04-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Joel P. de Souza ,  Bahman Hekmatshoartabari ,  Jeehwan Kim ,  Siegfried L. Maurer ,  Devendra K. Sadana

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  A23C9/123 ,  A23C11/08 ,  A23C9/13

CPC分类号： H01L21/283 ,  A23C9/123 ,  A23C9/1315 ,  A23C11/08 ,  H01L21/2254 ,  H01L21/28114 ,  H01L21/30604 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/32133 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66446 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

摘要： A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

公开(公告)号：US20180047896A1

公开(公告)日：2018-02-15

申请号：US15792842

申请日：2017-10-25

申请人： Micron Technology, Inc.

发明人： Marcello Ravasio ,  Samuele Sciarrillo ,  Andrea Gotti

IPC分类号： H01L45/00 ,  H01L21/3213 ,  H01L27/22 ,  H01L27/105 ,  H01L21/28 ,  H01L27/24

CPC分类号： H01L45/124 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/1052 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

公开(公告)号：US09893140B2

公开(公告)日：2018-02-13

申请号：US14915934

申请日：2015-09-16

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Xiaolong He ,  Feng Zhang ,  Zhanfeng Cao ,  Shi Shu ,  Yaohui Gu ,  Wei Xu ,  Miki Kashima

IPC分类号： H01L27/32 ,  H01L21/3213 ,  H01L21/308 ,  H01L51/56 ,  H01L51/00

CPC分类号： H01L27/3283 ,  H01L21/3083 ,  H01L21/3213 ,  H01L21/32139 ,  H01L51/0018 ,  H01L51/0023 ,  H01L51/56

摘要： The present disclosure provides a display panel separation pillar and a method for manufacturing the same, a display panel and a display device. The display panel separation pillar includes a first material pattern and a second material pattern on the first material pattern. The first material pattern includes an upper surface and a lower surface opposite to each other, and a first separation lateral side and a second separation lateral side which are opposite to each other and between the upper surface and the lower surface. The second material pattern includes an upper surface and a lower surface opposite to each other. The upper surface of the first material pattern directly contacts with the lower surface of the second material pattern. Projections of the first separation lateral side and the second separation lateral side of the first material pattern onto a plane of the lower surface of the second material pattern are between edges of the lower surface of the second material pattern.