公开(公告)号：US08346027B2

公开(公告)日：2013-01-01

申请号：US12816550

申请日：2010-06-16

Applicant: Jeong Woo Park ,  Jongbum You ,  Gyungock Kim

Inventor： Jeong Woo Park ,  Jongbum You ,  Gyungock Kim

IPC: G02F1/035

CPC classification number: G02F1/2257 ,  G02F1/015 ,  G02F2001/212

Abstract: Provided is an electro-optic device. The electro-optic device includes an input Y-branch comprising a first input branch and a second input branch, an output Y-branch comprising a first output branch and a second output branch, a first optical modulator and a second optical modulator connected in series between the first input branch and the first output branch, and a third optical modulator connecting the second input branch to the second output branch. The first optical modulator comprises a PIN diode, and each of the second optical modulator and the third optical modulator comprises a PN diode.

Abstract translation: 提供了一种电光装置。 电光装置包括：输入Y分支，包括第一输入分支和第二输入分支，包括第一输出分支和第二输出分支的输出Y分支，串联连接的第一光调制器和第二光调制器 在第一输入分支和第一输出分支之间，以及将第二输入分支连接到第二输出分支的第三光调制器。 第一光调制器包括PIN二极管，并且第二光调制器和第三光调制器中的每一个包括PN二极管。

公开(公告)号：US08346026B2

公开(公告)日：2013-01-01

申请号：US12517802

申请日：2007-08-07

Applicant: Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

Inventor： Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

IPC: G02F1/035 ,  G02B6/12 ,  G02B6/00

CPC classification number: H01L31/12 ,  H01L27/144

Abstract: Provided are a photoelectric device using a PN diode and a silicon integrated circuit (IC) including the photoelectric device. The photoelectric device includes: a substrate; and an optical waveguide formed as a PN diode on the substrate, wherein a junction interface of the PN diode is formed in a direction in which light advances; and an electrode applying a reverse voltage to the PN diode, wherein N-type and P-type semiconductors of the PN diode are doped at high concentrations and the doping concentration of the N-type semiconductor is higher than or equal to that of the P-type semiconductor.

Abstract translation: 提供了使用PN二极管的光电装置和包括光电装置的硅集成电路（IC）。 光电装置包括：基板; 以及在所述衬底上形成为PN二极管的光波导，其中所述PN二极管的结界面沿光前进的方向形成; 以及向PN二极管施加反向电压的电极，其中PN二极管的N型和P型半导体以高浓度掺杂，并且N型半导体的掺杂浓度高于或等于P 型半导体。

公开(公告)号：US20120295434A1

公开(公告)日：2012-11-22

申请号：US13473728

申请日：2012-05-17

Applicant: Moon-gi CHO ,  Sang-hee LEE ,  Jeong-woo PARK

Inventor： Moon-gi CHO ,  Sang-hee LEE ,  Jeong-woo PARK

IPC: H01L21/768

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01046

Abstract: A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.

Abstract translation: 一种形成具有减少的焊料凹陷的半导体器件的凸块的方法。 该方法包括制备其中焊盘从钝化层向外暴露的半导体衬底; 在半导体衬底上形成晶种层; 形成光致抗蚀剂图案以暴露焊盘上的种子层; 通过在由光致抗蚀剂图案曝光的区域上执行初级电镀形成柱; 通过在柱上进行二次电镀形成焊料层; 去除光致抗蚀剂图案; 通过对半导体衬底进行回流处理，形成焊料凸点，其中焊料部分地覆盖柱的表面; 以及除去形成在除了焊锡凸块之外的区域中的种子层的部分。

公开(公告)号：US20120292195A1

公开(公告)日：2012-11-22

申请号：US13438020

申请日：2012-04-03

Applicant: Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

Inventor： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

IPC: C25B15/00 ,  C25B9/00

CPC classification number: C25D17/001 ,  C25D5/02 ,  C25D5/08 ,  C25D7/123 ,  C25D17/008 ,  H01L21/2885

Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.

Abstract translation: 一种用于电镀半导体器件的设备包括一个容纳电镀溶液的电镀液和一个在电镀槽中的一个电极板，该电极板包括多个孔，该多个孔被配置成将电镀液通过桨向衬底通过，电镀液流动加强 所述部分被配置为选择性地将所述电镀溶液的流动加强到所述基板的预定区域，所述基板的所述预定区域是需要相对增加所述电镀液的金属离子供应的区域。

公开(公告)号：US20120148244A1

公开(公告)日：2012-06-14

申请号：US13302371

申请日：2011-11-22

Applicant: Sahnggi PARK ,  Gyungock KIM ,  In Gyoo KIM ,  Jeong Woo PARK ,  Sang Hoon KIM ,  Do Won KIM

Inventor： Sahnggi PARK ,  Gyungock KIM ,  In Gyoo KIM ,  Jeong Woo PARK ,  Sang Hoon KIM ,  Do Won KIM

IPC: H04J14/02

CPC classification number: H04J14/028 ,  G02B6/12007 ,  H01S5/026 ,  H01S5/1032 ,  H01S5/4087 ,  H04J14/02 ,  H04J14/0201

Abstract: Provided is an optical network structure. To configure an optical network structure between hundreds or more of cores in a CPU, intersection between waveguides does not occur, and thus, the optical network structure enables two-way communication between all the cores without an optical switch disposed in an intersection point. The present invention enables a single chip optical network using a silicon photonics optical element, and a CPU chip configured with hundreds or thousands of cores can be developed.

Abstract translation: 提供了一种光网络结构。 为了在CPU中配置数百个或更多个核心之间的光网络结构，不会发生波导之间的交叉，因此，光网络结构在所有核心之间实现双向通信，而光交换机不设置在交叉点。 本发明使得能够使用硅光子学光学元件的单芯片光网络，并且可以开发配置有数百或数千个核的CPU芯片。

公开(公告)号：US20120086123A1

公开(公告)日：2012-04-12

申请号：US13242864

申请日：2011-09-23

Applicant: JEONG-WOO PARK ,  MOON-GI CHO ,  UI-HYOUNG LEE ,  SUN-HEE PARK

Inventor： JEONG-WOO PARK ,  MOON-GI CHO ,  UI-HYOUNG LEE ,  SUN-HEE PARK

IPC: H01L23/498

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13193 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract translation: 提供了通过凸块将半导体芯片连接到外部设备的半导体封装。 半导体封装可以包括半导体芯片上的连接焊盘，连接焊盘，并且构造成电连接到连接焊盘，并且在半导体芯片上具有支撑突起，并且被配置为与连接焊盘电隔离。 连接凸起可以包括第一柱和第一焊球，并且支撑凸起可以包括第二柱和第二焊球。 半导体封装还可以包括在第二柱中的焊料通道，其被配置为允许第二焊球的一部分沿着预定方向延伸到焊料通道中。

公开(公告)号：US20120060365A1

公开(公告)日：2012-03-15

申请号：US13373387

申请日：2011-11-14

Applicant: Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

Inventor： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

IPC: H05K3/00

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern; forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer; preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer; removing the first and second carriers; and removing the first and second barrier layers.

Abstract translation: 一种制造具有金属凸块的印刷电路板的方法，包括：在第一载体上形成用于形成金属凸块的凹部，在第一载体上形成第一阻挡层，并在第一阻挡层上形成上电路层 所述上电路层包括充电在所述凹部中的金属凸块和电路图案; 在第二载体上形成第二阻挡层，并在第二阻挡层上形成下电路层; 制备绝缘层，并将上下电路层转移到绝缘层; 移除第一和第二载体; 以及去除所述第一和第二阻挡层。

公开(公告)号：US20110259627A1

公开(公告)日：2011-10-27

申请号：US13067883

申请日：2011-07-01

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.

Abstract translation: 电路板包括：具有凹槽的绝缘体; 填充所述凹槽的一部分的电路层; 电路层上的填充凹槽其余部分的焊盘; 以及与电路层电连接的电路图案，电路图案埋在绝缘体中，使得电路图案的一部分在绝缘体的表面露出。

公开(公告)号：US07970806B2

公开(公告)日：2011-06-28

申请号：US12015878

申请日：2008-01-17

Applicant: Jeong-woo Park ,  Gwang-ok Go ,  Jun-young Cho

Inventor： Jeong-woo Park ,  Gwang-ok Go ,  Jun-young Cho

IPC: G06F17/30

CPC classification number: G06F17/30218 ,  G06F3/0608 ,  G06F3/0643 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/7207

Abstract: Management of files in a memory, such as a flash memory, includes storing in the memory a first node including a first type of metadata of the file, a second node including data of the file and a third node including a second type of metadata of the file including file status and memory location information for the first and second nodes. The third node may include a node including memory location information for the second node and a node including an index table that cross-references a memory location for the memory location information for the second node to a memory location of the first node. Methods and devices may be provided.

Abstract translation: 管理诸如闪速存储器的存储器中的文件包括在存储器中存储包括文件的第一类型的元数据的第一节点，包括文件的数据的第二节点和包括文件的第二类型的第二类型的元数据 该文件包括用于第一和第二节点的文件状态和存储位置信息。 第三节点可以包括包括用于第二节点的存储器位置信息的节点和包括索引表的节点，所述索引表将用于第二节点的存储器位置信息的存储器位置交叉引用到第一节点的存储器位置。 可以提供方法和装置。

公开(公告)号：US07928442B2

公开(公告)日：2011-04-19

申请号：US12441381

申请日：2007-08-17

Applicant: Bongki Mheen ,  Jeong-Woo Park ,  Hyun-Soo Kim ,  Gyungock Kim

Inventor： Bongki Mheen ,  Jeong-Woo Park ,  Hyun-Soo Kim ,  Gyungock Kim

IPC: H01L31/036

CPC classification number: G02F1/025 ,  G02F1/2257 ,  H01L33/0037

Abstract: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area.

Abstract translation: 提供了具有应变埋入通道区域的光学装置。 该光学器件包括：第一导电类型的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上的与第一导电类型相反的第二导电类型的栅极; 形成在所述半导体衬底下的高密度掺杂剂扩散区，并且掺杂有比所述半导体衬底更高密度的第一导电型掺杂剂; 由半导体材料形成的应变掩埋沟道区域，具有与形成半导体衬底的材料不同的晶格参数，并且在栅极绝缘层和半导体衬底之间延伸以接触高密度掺杂剂扩散区域; 以及形成在栅绝缘层和应变埋入沟道区之间的半导体盖层。