公开(公告)号：US09312213B2

公开(公告)日：2016-04-12

申请号：US14014300

申请日：2013-08-29

Applicant: Moon Gi Cho ,  Young Lyong Kim ,  Sun-Hee Park ,  Hwan-Sik Lim

Inventor： Moon Gi Cho ,  Young Lyong Kim ,  Sun-Hee Park ,  Hwan-Sik Lim

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/0556 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13008 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.

Abstract translation: 凸块结构可以包括与设置在基板上的焊盘间隔开的主体部分和从主体部分的侧面延伸到焊盘上的第一延伸部。 第二延伸部从主体部分的另一侧延伸。

公开(公告)号：US20090212422A1

公开(公告)日：2009-08-27

申请号：US12182180

申请日：2008-07-30

Applicant: Hyuck Mo LEE ,  Moon Gi CHO ,  Dong Hoon KIM

Inventor： Hyuck Mo LEE ,  Moon Gi CHO ,  Dong Hoon KIM

IPC: H01L23/488 ,  B32B15/00

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10253 ,  H05K3/244 ,  H05K3/3463 ,  Y10T428/12493 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An improvement of joint reliability between Sn-yAg (0≦y≦4.0) solder and Ni—P under-bump metallic layers is achieved by cobalt (Co) addition. A solder joint with improved joint reliability is formed between a solder part of an electronic packaging and an under-bump metallic (UBM) layer, which has a specific structure comprising Sn-yAg-xCo (0.02≦x≦0.1, 0≦y≦4.0) alloy solder containing cobalt (Co) ingredient bonded to a Ni—P UBM. Also, a solder joint with a joint structure comprising Sn-yAg-xCo (0.02≦x≦0.1, 0≦y≦4.0) alloy solder with addition of Co ingredient and Ni—P UBM is formed, which is inserted between a PCB substrate and a silicon chip to join the same.

Abstract translation: 通过钴（Co）添加实现Sn-yAg（0 <= y <= 4.0）焊料和Ni-P凸块之间的金属层的连接可靠性的提高。 在电子封装的焊料部分和凸块之间的金属（UBM）层之间形成具有改进的接头可靠性的焊点，该焊接部分具有包含Sn-yAg-xCo（0.02 <= x <= 0.1,0 < = y <= 4.0）合金焊料，其含有结合到Ni-P UBM的钴（Co）成分。 此外，形成具有添加有Co成分和Ni-P UBM的Sn-yAg-xCo（0.02 <= x <= 0.1,0 <= y <= 4.0）合金焊料的接合结构的焊点，其被插入 在PCB基板和硅芯片之间加入它们。

公开(公告)号：US08710657B2

公开(公告)日：2014-04-29

申请号：US13242864

申请日：2011-09-23

Applicant: Jeong-woo Park ,  Moon-gi Cho ,  Ui-hyoung Lee ,  Sun-hee Park

Inventor： Jeong-woo Park ,  Moon-gi Cho ,  Ui-hyoung Lee ,  Sun-hee Park

IPC: H01L21/44

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13193 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract translation: 提供了通过凸块将半导体芯片连接到外部设备的半导体封装。 半导体封装可以包括半导体芯片上的连接焊盘，连接焊盘，并且构造成电连接到连接焊盘，并且在半导体芯片上具有支撑突起，并且被配置为与连接焊盘电隔离。 连接凸起可以包括第一柱和第一焊球，并且支撑凸起可以包括第二柱和第二焊球。 半导体封装还可以包括在第二柱中的焊料通道，其被配置为允许第二焊球的一部分沿着预定方向延伸到焊料通道中。

公开(公告)号：US20130009286A1

公开(公告)日：2013-01-10

申请号：US13471735

申请日：2012-05-15

Applicant: Young-lyong Kim ,  Jong-ho Lee ,  Moon-gi Cho ,  Hwan-sik Lim ,  Sun-hee Park

Inventor： Young-lyong Kim ,  Jong-ho Lee ,  Moon-gi Cho ,  Hwan-sik Lim ,  Sun-hee Park

IPC: H01L23/58

CPC classification number: H01L24/11 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/02123 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/0519 ,  H01L2224/05191 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/0556 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05666 ,  H01L2224/0569 ,  H01L2224/05691 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/14131 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Abstract translation: 半导体芯片包括减轻压力以减轻印刷电路板（PCB）和半导体芯片之间的热膨胀系数（CTE）的差异以及包括半导体芯片的倒装芯片封装的影响。 半导体芯片包括耦合凸块的应力消除缓冲器和半导体芯片焊盘。

公开(公告)号：US20120295434A1

公开(公告)日：2012-11-22

申请号：US13473728

申请日：2012-05-17

Applicant: Moon-gi CHO ,  Sang-hee LEE ,  Jeong-woo PARK

Inventor： Moon-gi CHO ,  Sang-hee LEE ,  Jeong-woo PARK

IPC: H01L21/768

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01046

Abstract: A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.

Abstract translation: 一种形成具有减少的焊料凹陷的半导体器件的凸块的方法。 该方法包括制备其中焊盘从钝化层向外暴露的半导体衬底; 在半导体衬底上形成晶种层; 形成光致抗蚀剂图案以暴露焊盘上的种子层; 通过在由光致抗蚀剂图案曝光的区域上执行初级电镀形成柱; 通过在柱上进行二次电镀形成焊料层; 去除光致抗蚀剂图案; 通过对半导体衬底进行回流处理，形成焊料凸点，其中焊料部分地覆盖柱的表面; 以及除去形成在除了焊锡凸块之外的区域中的种子层的部分。

公开(公告)号：US20120086123A1

公开(公告)日：2012-04-12

申请号：US13242864

申请日：2011-09-23

Applicant: JEONG-WOO PARK ,  MOON-GI CHO ,  UI-HYOUNG LEE ,  SUN-HEE PARK

Inventor： JEONG-WOO PARK ,  MOON-GI CHO ,  UI-HYOUNG LEE ,  SUN-HEE PARK

IPC: H01L23/498

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13193 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract translation: 提供了通过凸块将半导体芯片连接到外部设备的半导体封装。 半导体封装可以包括半导体芯片上的连接焊盘，连接焊盘，并且构造成电连接到连接焊盘，并且在半导体芯片上具有支撑突起，并且被配置为与连接焊盘电隔离。 连接凸起可以包括第一柱和第一焊球，并且支撑凸起可以包括第二柱和第二焊球。 半导体封装还可以包括在第二柱中的焊料通道，其被配置为允许第二焊球的一部分沿着预定方向延伸到焊料通道中。

公开(公告)号：US20150364387A1

公开(公告)日：2015-12-17

申请号：US14729034

申请日：2015-06-02

Applicant: Moon-gi CHO ,  Eun-chul AHN ,  Jung-ho CHOI

Inventor： Moon-gi CHO ,  Eun-chul AHN ,  Jung-ho CHOI

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/304

CPC classification number: H01L22/20 ,  B24B37/005 ,  B24B37/042 ,  B24B49/12 ,  H01L21/02016 ,  H01L21/02024 ,  H01L22/12

Abstract: A wafer polishing method includes first polishing for polishing a wafer backside of a wafer, detecting if a defect exists on the wafer backside, determining whether a level of the detected defect is not within an allowable range, if a defect exists on the wafer backside, and second polishing for repolishing the wafer backside if the level of the defect is within an allowable range. Accordingly, a wafer may be reprocessed so that a level of defects, which may be caused by performing grinding and polishing on the wafer backside, is within an allowable range. Thus, the wafer backside may have uniform quality, and a failure rate of the wafer during a manufacturing processed may be efficiently decreased.

Abstract translation: 晶片抛光方法包括：第一抛光用于抛光晶片的晶片背面，检测晶片背面是否存在缺陷;如果在晶片背面存在缺陷，则确定检测到的缺陷的水平是否不在容许范围内; 以及如果缺陷水平在允许范围内，则再次抛光晶片背面的第二抛光。 因此，可以对晶片进行再处理，使得可以通过在晶片背面进行研磨和研磨而引起的缺陷水平在允许范围内。 因此，晶片背面可以具有均匀的质量，并且可以有效地降低在制造加工期间晶片的故障率。

公开(公告)号：US08980739B2

公开(公告)日：2015-03-17

申请号：US13473728

申请日：2012-05-17

Applicant: Moon-gi Cho ,  Sang-hee Lee ,  Jeong-woo Park

Inventor： Moon-gi Cho ,  Sang-hee Lee ,  Jeong-woo Park

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/01029 ,  H01L2924/01046

Abstract: A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.

Abstract translation: 一种形成具有减少的焊料凹陷的半导体器件的凸块的方法。 该方法包括制备其中焊盘从钝化层向外暴露的半导体衬底; 在半导体衬底上形成晶种层; 形成光致抗蚀剂图案以暴露焊盘上的种子层; 通过在由光致抗蚀剂图案曝光的区域上执行初级电镀形成柱; 通过在柱上进行二次电镀形成焊料层; 去除光致抗蚀剂图案; 通过对半导体衬底进行回流处理，形成焊料凸点，其中焊料部分地覆盖柱的表面; 以及除去形成在除了焊锡凸块之外的区域中的种子层的部分。

公开(公告)号：US20120129333A1

公开(公告)日：2012-05-24

申请号：US13241824

申请日：2011-09-23

Applicant: Ha-Young YIM ,  Eun-Chul AHN ,  Ui-Hyoung LEE ,  Moon-Gi CHO ,  Hwan-Sik LIM

Inventor： Ha-Young YIM ,  Eun-Chul AHN ,  Ui-Hyoung LEE ,  Moon-Gi CHO ,  Hwan-Sik LIM

IPC: H01L21/60 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76804 ,  H01L21/76885 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11912 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

Abstract: Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening.

Abstract translation: 提供一种使用该方法制造的半导体封装和半导体封装的制造方法。 该方法包括提供具有第一区域和第二区域的衬底，该第一区域和第二区域具有比第一区域更高的台阶差，即，具有高度差，形成具有暴露第一区域的一部分的第一开口的掩模图案， 打开所述基板上的所述第二区域的一部分，分别形成填充所述第一和第二开口的第一和第二凸块材料膜，并且通过对所述第一和第二凸块材料膜执行回流处理来形成所述第一和第二凸块，其中 第一开口具有与第二开口具有相同宽度的下部，并且具有大于第二开口的宽度的顶部。

公开(公告)号：US20130082090A1

公开(公告)日：2013-04-04

申请号：US13614608

申请日：2012-09-13

Applicant: Moon-gi CHO ,  Hwan-sik LIM ,  Sun-hee PARK

Inventor： Moon-gi CHO ,  Hwan-sik LIM ,  Sun-hee PARK

IPC: B23K31/02 ,  B23K1/20

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2924/014

Abstract: Methods of forming connection bumps for semiconductor devices in which rewiring patterns are formed. The method includes preparing a semiconductor substrate on which a pad is partially exposed through a passivation film, forming a seed layer on the pad and passivation film, forming a photoresist pattern including an opening pattern comprising a first opening that exposes a portion of the seed layer on the pad and a second opening that exposes a portion of the seed layer on the passivation film and is separated from the first opening, performing a first electroplating to form filler layers in the opening patterns, performing a second electroplating to form a solder layer on the filler layers, removing the photoresist pattern and performing a reflow process to form a collapsed solder layer that electrically connects the filler layers to each other and a solder bump on the filler layer formed in the second opening.

Abstract translation: 形成重新布线图形的半导体器件的连接凸块的形成方法。 该方法包括制备其上通过钝化膜部分地暴露焊盘的半导体衬底，在焊盘和钝化膜上形成种子层，形成包括开口图案的光致抗蚀剂图案，该开口图案包括暴露种子层的一部分的第一开口 在所述焊盘上和第二开口，其暴露所述钝化膜上的所述种子层的一部分并且与所述第一开口分离，执行第一电镀以在所述开口图案中形成填充层，执行第二电镀以形成焊料层 填充层，去除光致抗蚀剂图案并进行回流处理，以形成将填充层彼此电连接的凹陷焊料层和形成在第二开口中的填料层上的焊料凸块。