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    Method for controlling an integrated circuit
    611.
    发明授权
    Method for controlling an integrated circuit 有权
    控制集成电路的方法

    公开(公告)号：US09479168B2

    公开(公告)日：2016-10-25

    申请号：US14225520

    申请日：2014-03-26

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

    IPC: H03K19/096 ,  H03K19/00 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H03K19/0185

    CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

    Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

    Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

    Integrated hybrid laser source compatible with a silicon technology platform, and fabrication process
    613.
    发明授权
    Integrated hybrid laser source compatible with a silicon technology platform, and fabrication process 有权
    集成混合激光源兼容硅技术平台及制作工艺

    公开(公告)号：US09461441B2

    公开(公告)日：2016-10-04

    申请号：US14945859

    申请日：2015-11-19

    Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Alain Chantre ,  Charles Baudot ,  Sébastien Cremer

    IPC: H01S5/00 ,  H01S5/026 ,  H01S5/125 ,  H01S5/22 ,  H01S5/02 ,  H01S5/065

    CPC classification number: H01S5/026 ,  G02B6/12004 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/136 ,  H01S5/021 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0267 ,  H01S5/0268 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/0656 ,  H01S5/1032 ,  H01S5/1035 ,  H01S5/125 ,  H01S5/22 ,  H01S5/2206

    Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

    Abstract translation: 光子集成电路包括封装至少一个金属化水平的第一绝缘区域，至少部分地封装激光源的增益介质的第二绝缘区域和放置在两个绝缘区域之间的层叠结构。 层叠结构包括第一多晶或单晶硅层，第二多晶或单晶硅层，与激光源的波长光学兼容并且可相对于硅选择性地蚀刻的中间层，并且将第一层与 所述第二层的第一部分和所述增益介质面向所述第一层的至少一部分。 第一层，中间层和第二层的第一部分形成包含谐振腔和波导的组件，光学耦合到增益介质，第二层的第二部分包含至少一个其他光子 零件。

    Coplanar waveguide
    615.
    发明授权
    Coplanar waveguide 有权
    共面波导

    公开(公告)号：US09450280B2

    公开(公告)日：2016-09-20

    申请号：US14527249

    申请日：2014-10-29

    Applicant: STMicroelectronics SA

    Inventor： Sébastien Pruvost ,  Frederic Gianesello

    IPC: H01P3/08 ,  H01P3/00

    CPC classification number: H01P3/003 ,  H01P3/006 ,  H01P3/082

    Abstract: A coplanar waveguide electronic device is formed on a substrate. The waveguide includes a signal ribbon and a ground plane. The signal ribbon is formed of two or more signal lines of a same level of metallization that are electrically connected together. The ground plane is formed of an electrically conducting material which includes rows of holes.

    Abstract translation: 在基板上形成共面波导电子器件。 波导包括信号带和接地平面。 信号带由两个或更多个电连接在一起的相同金属化水平的信号线形成。 接地平面由导电材料形成，其包括一排孔。

    MULTI-ORIENTATION INTEGRATED CELL, IN PARTICULAR INPUT/OUTPUT CELL OF AN INTEGRATED CIRCUIT
    618.
    发明申请
    MULTI-ORIENTATION INTEGRATED CELL, IN PARTICULAR INPUT/OUTPUT CELL OF AN INTEGRATED CIRCUIT 有权
    多方向集成电路，集成电路的特殊输入/输出电路

    公开(公告)号：US20160134282A1

    公开(公告)日：2016-05-12

    申请号：US14865618

    申请日：2015-09-25

    Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Alexandre DRAY ,  Emmanuel Josse

    IPC: H03K17/687 ,  G01R31/28 ,  H01L21/66

    CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

    Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

    Abstract translation: 集成电路包括设置在集成电路的位置处的至少一个集成电池。 所述至少一个集成单元可以具有耦合到所述集成单元的至少一个站点和多路复用器的两个集成设备，并且所述两个集成设备分别定向在两个不同的取向方向上。 可以使用在两个取向方向中的一个方向上定向的两个集成装置的第一集成装置。 集成电路可以包括被配置为检测定向方向的控制器，其考虑到位置处的集成单元的布置可允许第一集成设备可用，并且控制多路复用器将第一集成设备 电连接至该至少一个位点。

    Method of stressing a semiconductor layer
    620.
    发明授权
    Method of stressing a semiconductor layer 有权
    强化半导体层的方法

    公开(公告)号：US09318372B2

    公开(公告)日：2016-04-19

    申请号：US14526053

    申请日：2014-10-28

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

    Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

    IPC: H01L21/00 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12 ,  H01L21/02

    CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

    Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

    Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

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