公开(公告)号：US08076183B2

公开(公告)日：2011-12-13

申请号：US12606290

申请日：2009-10-27

Applicant: Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

Inventor： Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L24/73 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.

Abstract translation: 公开了一种将引线框封装内的互连板连接到半导体管芯的方法。 基座引线框架设置有用于附接半导体管芯的管芯焊盘。 提供互连板，用于附接到基底引线框架和半导体管芯。 将基准注册功能添加到基准引线框架和板对准特征到互连板上，其中配准特征被设计成彼此匹配，使得在互连板到基底引线框架的接近时，两个配准特征将相互接合并引导彼此引起伴随 互连板与基座引线框架的自对准连接。 接下来，使互连板靠近基底引线框架以将板对准特征接合并锁定到基准对准特征，从而完成互连板连接到半导体管芯并形成引线框封装。

公开(公告)号：US20160056098A9

公开(公告)日：2016-02-25

申请号：US14204019

申请日：2014-03-11

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/49582 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83486 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/013 ,  H01L2924/05432 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

公开(公告)号：US09224669B2

公开(公告)日：2015-12-29

申请号：US14097433

申请日：2013-12-05

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/304 ,  H01L21/56

CPC classification number: H01L23/535 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract translation: 一种用于提供具有增加的接触焊盘区域的晶片级封装的方法，包括以下步骤：在晶片顶表面上形成第一封装层，研磨晶片背面并蚀刻通孔，沉积金属以填充通孔并覆盖晶片背面， 从晶片背面切割晶片，形成分开每个芯片的多个沟槽，然后沉积填充沟槽并覆盖晶片背面金属的第二封装层，减小第一封装层厚度以露出填充凹槽的第二封装层并形成多个 接触垫重叠在第一包装层上，然后切割槽中的第二包装层以形成单个包装。

公开(公告)号：US20150262925A1

公开(公告)日：2015-09-17

申请号：US14204019

申请日：2014-03-11

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/49582 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83486 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/013 ,  H01L2924/05432 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract translation: 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US09136379B2

公开(公告)日：2015-09-15

申请号：US13871144

申请日：2013-04-26

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Ping Huang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/42372 ,  H01L29/781 ,  H01L2224/04105 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/051 ,  H01L2224/05562 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

Abstract translation: 底部源极功率金属氧化物半导体场效应晶体管（MOSFET）器件包括形成在半导体芯片的第一表面上的初始绝缘层上的栅电极和源电极，以及形成在半导体芯片的第二表面上的漏电极 半导体芯片 源电极包括源极金属，形成在源极金属上的源极电极凸点和源极电极凸起顶部上的源电极金属层。 第一绝缘层覆盖栅电极。 从芯片的第二表面形成与栅电极对准的贯通孔，以将栅电极的一部分从第二表面露出。

公开(公告)号：US20150243589A1

公开(公告)日：2015-08-27

申请号：US14186275

申请日：2014-02-21

Applicant: Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

Inventor： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

IPC: H01L23/495 ,  H01L27/088

CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

公开(公告)号：US20150087114A1

公开(公告)日：2015-03-26

申请号：US14033140

申请日：2013-09-20

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495

CPC classification number: H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract translation: 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US08952509B1

公开(公告)日：2015-02-10

申请号：US14031283

申请日：2013-09-19

Applicant: Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

Inventor： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

IPC: H01L25/07 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.

Abstract translation: 本发明公开了一种叠层双MOSFET封装结构及其制备方法。 堆叠双MOSFET封装结构包括具有管芯焊盘，第一引线和第二引线的引线框架单元; 第一芯片翻转并附接在模板的主桨的顶表面上; 附接在主桨的底表面上的第二芯片; 以及安装在翻转的第一芯片的背面上并将第一芯片背面的电极电连接到第一引线的金属夹。 布置在第二芯片的前面的每个电极上的金属凸块的顶表面，模板的模具销的底表面，第二引线的引脚的底表面和第一引脚的底表面 导线位于同一平面上。

公开(公告)号：US08933518B2

公开(公告)日：2015-01-13

申请号：US13734201

申请日：2013-01-04

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC: H01L23/495 ,  H01L27/088 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L27/088 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Abstract translation: 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

公开(公告)号：US08890296B2

公开(公告)日：2014-11-18

申请号：US13750944

申请日：2013-01-25

Applicant: Yueh-Se Ho ,  Yan Xun Xue

Inventor： Yueh-Se Ho ,  Yan Xun Xue

IPC: H01L23/495 ,  H01L21/00 ,  H01L29/06 ,  H01L21/768 ,  H01L29/417 ,  H01L25/065 ,  H01L29/78 ,  H01L23/482 ,  H01L23/31 ,  H01L29/423 ,  H01L23/485 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Abstract translation: 描述半导体器件，制造半导体器件的方法和电路封装组件。 半导体器件可以具有带有第一和第二表面的半导体衬底和它们之间的侧壁。 第一和第二表面上的第一和第二导电焊盘与衬底中对应的第一和第二半导体器件结构电接触。 第一表面和侧壁上的绝缘体层覆盖第一表面上的第一导电焊盘的一部分。 在第一导电焊盘和侧壁上的绝缘体层的一部分上的导电层与第二导电焊盘电接触。 绝缘体层防止导电层在第一和第二导电焊盘之间形成电接触。