公开(公告)号：US20050168952A1

公开(公告)日：2005-08-04

申请号：US10974513

申请日：2004-10-26

申请人： Chin-Te Chen ,  Han-Ping Pu

发明人： Chin-Te Chen ,  Han-Ping Pu

IPC分类号： H01L23/04 ,  H01L23/10 ,  H05K7/20

CPC分类号： H01L23/04 ,  H01L23/10 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315

摘要： A semiconductor package includes a substrate; a chip mounted on a surface of the substrate; a lid having a flat portion and a support portion extending from the flat portion, wherein the support portion is attached to the substrate, with the chip being encompassed by the flat portion, the support portion and the substrate, and at least one cut-away portion is formed at an outer edge of a surface of the support portion attached to the substrate; an adhesive for attaching the lid to the substrate and filling the cut-away portion to allow an applied amount of the adhesive to be observed from the cut-away portion; and a plurality of solder balls mounted on another surface of the substrate. The applied amount of the adhesive can be adjusted optimally by provision of the cut-away portion to improve bonding strength between the lid and substrate and prevent flash of the adhesive.

摘要翻译： 半导体封装包括基板; 安装在基板的表面上的芯片; 具有平坦部分和从所述平坦部分延伸的支撑部分的盖，其中所述支撑部分附接到所述基板，所述芯片被所述平坦部分，所述支撑部分和所述基板包围，并且至少一个切除 部分形成在附着于基板的支撑部分的表面的外边缘处; 粘合剂，用于将盖子附接到基板并填充切除部分，以允许从切除部分观察涂布量的粘合剂; 以及安装在所述基板的另一表面上的多个焊球。 可以通过设置切除部分来最佳地调节粘合剂的施加量，以提高盖和基板之间的粘合强度并防止粘合剂的闪光。

公开(公告)号：US06891273B2

公开(公告)日：2005-05-10

申请号：US10404173

申请日：2003-04-01

申请人： Han-Ping Pu ,  Chien Ping Huang

发明人： Han-Ping Pu ,  Chien Ping Huang

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

摘要翻译： 提供了一种半导体封装及其制造方法，其中芯片安装在基板上，并且电介质层被施加在基板和芯片上，具有形成在基板上的结合指状物，并且形成在芯片上的电触点暴露在外部。 在电介质层和暴露的结合指状物和电触点之上形成金属层，并且被图案化以形成将芯片的电触头电连接到衬底的结合指的多个导电迹线。 导电迹线取代了传统的引线键合技术，从而消除了制造工艺中线扫或短路的发生。 因此，可以使用在相邻的电触点之间具有减小的间距的低轮廓芯片，而不限于引线接合技术的可行性。

公开(公告)号：US06593662B1

公开(公告)日：2003-07-15

申请号：US09631343

申请日：2000-08-02

申请人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

发明人： Han-Ping Pu ,  Randy H. Y. Lo ,  Tzong-Dar Her ,  Chien-Ping Huang ,  Cheng-Shiu Hsiao ,  Chi-Chuan Wu

IPC分类号： H01L2348

CPC分类号： H01L24/33 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by one on the upper surface of the carrier, and a number of bonding pads are located around each die. The spacers are located between two adjacent dies. Adhesive layers located between the spacers, the dies, and the carrier for adhering layers therebetween. The conducting lines are respectively electrically connected between each of the bonding pads of the dies and the carrier. And the mold compound is formed over the upper surface of the carrier, for encapsulating the spacers, the dies and the adhesive layers. A substrate with solder balls or a lead frame having pins is suitable for serving as the carrier.

摘要翻译： 堆叠管芯封装结构包括载体，管芯，间隔物，粘合剂层，导电线，模具化合物和焊球。 载体具有与上表面相对的上表面和后表面。 基本上具有相同尺寸的模具在载体的上表面上一个接一个堆叠，并且多个焊盘位于每个管芯周围。 间隔件位于两个相邻的模具之间。 位于间隔件，模具和载体之间的粘合层，用于在其间粘合层。 导体线分别电连接在管芯和载体的每个接合焊盘之间。 并且模制化合物形成在载体的上表面上，用于封装间隔物，模具和粘合剂层。 具有焊球或具有引脚的引线框架的基板适合用作载体。

公开(公告)号：US06469897B2

公开(公告)日：2002-10-22

申请号：US09774211

申请日：2001-01-30

申请人： Tzong-Da Ho ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Tzong-Da Ho ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H05K720

CPC分类号： H01L23/49816 ,  H01L23/36 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  Y10T29/4935 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A TBGA (Tape Ball Grid Array) package assembly with grounded heat sink and method of fabricating the same is provided, which is constructed of a tape, a heat sink, and at least one semiconductor chip. The proposed TBGA technology is characterized by that a grounding plug is formed by first forming a via hole in the heat sink and a via hole in the tape without penetrating through the grounding solder-ball pad, and then filling an electrically-conductive material, such as solder or silver paste, into the heat-sink via hole from the top of the package assembly until filling up the tape via hole and the heat-sink via hole. As the semiconductor chip is mounted in position, its grounding pads are electrically bonded to the heat sink, thereby allowing the semiconductor chip to be externally grounded through the grounding plug, the grounding solder-ball pad, and the solder ball attached to the grounding solder-ball pad. The proposed TBGA technology allows the resulted grounding plug to be firmly secured in position due to the filled solder being wettable to the heat sink, thereby providing a greater ball shear strength to the grounding solder ball that is subsequently bonded to the grounding plug. The finished TBGA package would be therefore assured in the reliability of its grounding structure.

公开(公告)号：US06400036B1

公开(公告)日：2002-06-04

申请号：US09920069

申请日：2001-08-01

申请人： Wei-Sen Tang ,  Han-Ping Pu

发明人： Wei-Sen Tang ,  Han-Ping Pu

IPC分类号： H01L2144

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/28 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.

摘要翻译： 提出了一种倒装芯片封装技术，用于制造双芯片集成电路封装，其包括在单个封装单元中的两个半导体芯片，其特征在于形成闪光屏障结构，其可以帮助防止使用的底部填充材料 在从闪烁到其他非预期区域的倒装芯片底部填充过程中。 闪光屏障结构可以是下面的半导体芯片上的突出的坝结构，也可以是形成在下面的半导体芯片上的涂层中的凹槽。 在倒装芯片底部填充过程中，闪光屏障结构可以将底部填充材料限制在预期区域内，并防止底部填充材料流到其他非预期区域（例如附近的焊盘），从而可以确保成品包装产品的质量和 可靠性。

公开(公告)号：US09041223B2

公开(公告)日：2015-05-26

申请号：US13610050

申请日：2012-09-11

申请人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

发明人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/40 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/44 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

摘要翻译： 描述了跟踪（BOT）结构。 BOT结构包括在第一工件的表面上具有金属迹线的第一工件，其中金属迹线具有第一轴线。 BOT结构还包括具有细长金属凸块的第二工件，其中细长金属凸块具有第二轴线，其中第二轴线与第一轴线成非零角度。 BOT结构还包括金属凸块，其中金属凸块电连接金属迹线和细长金属凸块。 还描述了具有BOT结构的封装和形成BOT结构的方法。

公开(公告)号：US08400178B2

公开(公告)日：2013-03-19

申请号：US12431927

申请日：2009-04-29

申请人： Han-Ping Pu ,  Mill-Jer Wang

发明人： Han-Ping Pu ,  Mill-Jer Wang

IPC分类号： G01R31/02

CPC分类号： H01L23/345 ,  G01R31/2856 ,  G01R31/2875 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device, the device includes a substrate, a front-end structure formed in the substrate, a back-end structure formed on the front-end structure, a heater embedded in the back-end structure and operable to generate heat, and a sensor embedded in the back-end structure and operable to sense a temperature of the semiconductor device.

摘要翻译： 本公开提供一种半导体器件，该器件包括衬底，形成在衬底中的前端结构，形成在前端结构上的后端结构，嵌入在后端结构中的加热器，可操作以产生 热和嵌入在后端结构中的传感器，并且可操作以感测半导体器件的温度。

公开(公告)号：US20120306067A1

公开(公告)日：2012-12-06

申请号：US13151720

申请日：2011-06-02

申请人： Pei-Haw Tsao ,  Kuo-Chin Chang ,  Han-Ping Pu

发明人： Pei-Haw Tsao ,  Kuo-Chin Chang ,  Han-Ping Pu

IPC分类号： H01L23/488 ,  H01L23/36 ,  H01L21/50

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/00

摘要： According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.

摘要翻译： 根据实施例，集成电路封装包括芯片，热部件和模制化合物。 芯片包括有源表面和与有源表面相对的背面。 热分量物理耦合到芯片的背面。 模塑料包封芯片，并且通过模塑料露出热组分的暴露表面。 另一实施例是形成集成电路封装的方法。

公开(公告)号：US20070296079A1

公开(公告)日：2007-12-27

申请号：US11818225

申请日：2007-06-12

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

IPC分类号： H01L23/34 ,  H01L21/58

CPC分类号： H01L23/4334 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first heat dissipating element having a heat dissipating portion and a supporting portion onto the chip carrier. The method further includes forming openings corresponding to the semiconductor chip in the heat dissipating portion, and forming an encapsulant for covering the semiconductor chip, the interface layer or the second heat dissipating element, and the first heat dissipating element. A height is reserved on top of the interface layer for the formation of the encapsulant for covering the interface layer. The method further includes cutting the encapsulant along edges of the interface layer, and removing the redundant encapsulant on the interface layer. Therefore, the drawbacks of the prior art of the burrs caused by a cutting tool for cutting the heat dissipating element and wearing of the cutting tool are overcome.

摘要翻译： 公开了一种散热器封装结构及其制造方法。 该方法包括将半导体芯片安装并电连接到芯片载体，在半导体芯片上形成具有界面层的界面层或第二散热元件，并将具有散热部分和支撑部分的第一散热元件安装到 芯片载体。 该方法还包括形成对应于散热部分中的半导体芯片的开口，以及形成用于覆盖半导体芯片，界面层或第二散热元件的密封剂和第一散热元件。 在接口层顶部保留一个高度，用于形成覆盖界面层的密封剂。 该方法还包括沿着界面层的边缘切割密封剂，以及去除界面层上的冗余密封剂。 因此，克服了用于切割散热元件的切削工具和切削工具的磨损引起的毛刺现有技术的缺陷。

公开(公告)号：US07247934B2

公开(公告)日：2007-07-24

申请号：US11026933

申请日：2004-12-29

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H05K1/141 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10689 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

摘要翻译： 提供一种多芯片半导体封装及其制造方法。 至少一个第一芯片通过焊料凸块安装在基板的上表面上并电连接到基板的上表面。 具有第二芯片和第一封装体的预制封装结构安装在基板的上表面上，其中预成型封装结构的外引线从第一封装体露出并电连接到基板的上表面。 第一封装体，外引线和衬底形成接收第一芯片的空间，并且在第一芯片和第一封装体之间存在间隙。 第二封装体形成在衬底的上表面上，以封装第一芯片，焊料凸块和预成型封装结构。 在基板的下表面上注入多个焊球。