公开(公告)号：US06980438B2

公开(公告)日：2005-12-27

申请号：US10759863

申请日：2004-01-16

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/055 ,  H01L23/10 ,  H01L23/367 ,  H01L23/467 ,  H01L25/065 ,  H05K7/20

CPC分类号： H01L23/467 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/055 ,  H01L23/10 ,  H01L23/3672 ,  H01L23/3675 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor package with a heat dissipating structure includes a substrate, a chip and a heat dissipating structure. The chip is mounted on and electrically connected to the substrate. The heat dissipating structure includes a first heat sink having at least one positioning portion, and at least one second heat sink having at least one second positioning portion and at least one hollow portion. The second heat sink is mounted on the substrate, and the first positioning portion of the first heat sink is attached to the second positioning portion of the second heat sink, allowing the chip to be accommodated in a space defined by the first heat sink, the hollow portion of the second heat sink and the substrate. This semiconductor package has good heat dissipating efficiency and is cost-effective to fabricate.

公开(公告)号：US20050168952A1

公开(公告)日：2005-08-04

申请号：US10974513

申请日：2004-10-26

申请人： Chin-Te Chen ,  Han-Ping Pu

发明人： Chin-Te Chen ,  Han-Ping Pu

IPC分类号： H01L23/04 ,  H01L23/10 ,  H05K7/20

CPC分类号： H01L23/04 ,  H01L23/10 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315

摘要： A semiconductor package includes a substrate; a chip mounted on a surface of the substrate; a lid having a flat portion and a support portion extending from the flat portion, wherein the support portion is attached to the substrate, with the chip being encompassed by the flat portion, the support portion and the substrate, and at least one cut-away portion is formed at an outer edge of a surface of the support portion attached to the substrate; an adhesive for attaching the lid to the substrate and filling the cut-away portion to allow an applied amount of the adhesive to be observed from the cut-away portion; and a plurality of solder balls mounted on another surface of the substrate. The applied amount of the adhesive can be adjusted optimally by provision of the cut-away portion to improve bonding strength between the lid and substrate and prevent flash of the adhesive.

摘要翻译： 半导体封装包括基板; 安装在基板的表面上的芯片; 具有平坦部分和从所述平坦部分延伸的支撑部分的盖，其中所述支撑部分附接到所述基板，所述芯片被所述平坦部分，所述支撑部分和所述基板包围，并且至少一个切除 部分形成在附着于基板的支撑部分的表面的外边缘处; 粘合剂，用于将盖子附接到基板并填充切除部分，以允许从切除部分观察涂布量的粘合剂; 以及安装在所述基板的另一表面上的多个焊球。 可以通过设置切除部分来最佳地调节粘合剂的施加量，以提高盖和基板之间的粘合强度并防止粘合剂的闪光。

公开(公告)号：US20050036291A1

公开(公告)日：2005-02-17

申请号：US10759863

申请日：2004-01-16

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Chin-Te Chen ,  Chang-Fu Lin

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/055 ,  H01L23/10 ,  H01L23/367 ,  H01L23/467 ,  H01L25/065 ,  H05K7/20

CPC分类号： H01L23/467 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/055 ,  H01L23/10 ,  H01L23/3672 ,  H01L23/3675 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor package with a heat dissipating structure includes a substrate, a chip and a heat dissipating structure. The chip is mounted on and electrically connected to the substrate. The heat dissipating structure includes a first heat sink having at least one positioning portion, and at least one second heat sink having at least one second positioning portion and at least one hollow portion. The second heat sink is mounted on the substrate, and the first positioning portion of the first heat sink is attached to the second positioning portion of the second heat sink, allowing the chip to be accommodated in a space defined by the first heat sink, the hollow portion of the second heat sink and the substrate. This semiconductor package has good heat dissipating efficiency and is cost-effective to fabricate.

摘要翻译： 具有散热结构的半导体封装包括基板，芯片和散热结构。 芯片安装在基板上并电连接到基板。 散热结构包括具有至少一个定位部分的第一散热器和具有至少一个第二定位部分和至少一个中空部分的至少一个第二散热器。 第二散热器安装在基板上，并且第一散热器的第一定位部分附接到第二散热器的第二定位部分，允许芯片容纳在由第一散热器限定的空间中， 第二散热器的中空部分和基板。 该半导体封装具有良好的散热效率，并且制造成本低。

公开(公告)号：US20060214308A1

公开(公告)日：2006-09-28

申请号：US11347735

申请日：2006-02-02

申请人： Kuo-Hua Yu ,  Chin-Te Chen ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Kuo-Hua Yu ,  Chin-Te Chen ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/4951 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16245 ,  H01L2224/81011 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A flip-chip semiconductor package and a method for fabricating the same are proposed. A flux is formed on surfaces of solder bumps mounted on an active surface of a semiconductor chip, wherein the acid number of the flux is greater than 20 and the viscosity of the flux is greater than 40. When the chip is electrically connected to a lead frame via the solder bumps by a reflowing process, the flux allows the chip to be effectively fixed to the lead frame and makes the solder bumps not easily wetted to the lead frame during the reflowing process, so as to prevent over-collapsing of the solder bumps.

摘要翻译： 提出了一种倒装芯片半导体封装及其制造方法。 在安装在半导体芯片的有源表面上的焊料凸块的表面上形成焊剂，其中焊剂的酸值大于20，焊剂的粘度大于40。当芯片电连接到引线 通过回流工艺通过焊料凸块框架，焊剂允许芯片有效地固定到引线框架，并且使得焊料凸块在回流过程中不容易地被润湿到引线框架，以防止焊料的过度塌陷 颠簸

公开(公告)号：US09978656B2

公开(公告)日：2018-05-22

申请号：US13406270

申请日：2012-02-27

申请人： Tsung-Shu Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Chang-Chia Huang ,  Hao-Juin Liu

发明人： Tsung-Shu Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Chang-Chia Huang ,  Hao-Juin Liu

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/293 ,  H01L21/568 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16237 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.

公开(公告)号：US09502360B2

公开(公告)日：2016-11-22

申请号：US13348449

申请日：2012-01-11

申请人： Chun-Hung Lin ,  Yu-Feng Chen ,  Han-Ping Pu ,  Hung-Jui Kuo

发明人： Chun-Hung Lin ,  Yu-Feng Chen ,  Han-Ping Pu ,  Hung-Jui Kuo

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L23/562 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00

摘要： A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.

摘要翻译： 提供了用于包装的应力补偿，以及形成方法。 应力补偿层从集成电路管芯放置在衬底的相对侧上。 应力补偿层被设计成抵抗基板的模具侧上的应力施加结构中的至少一些，例如由至少部分地封装第一集成电路管芯的模制化合物施加的应力。 封装还可以电耦合到衬底。

公开(公告)号：US09418947B2

公开(公告)日：2016-08-16

申请号：US13406031

申请日：2012-02-27

申请人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Kai-Chiang Wu

发明人： Yu-Feng Chen ,  Chun-Hung Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Kai-Chiang Wu

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03334 ,  H01L2224/0384 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2224/05552

摘要： The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

摘要翻译： 所描述的形成用于封装封装的连接器的机构的实施例使得具有更细间距的较小连接器能够实现更小的封装尺寸和附加的连接。 一个封装上的导电元件部分地嵌入封装的模制化合物中，以与另一封装上的触点或金属焊盘结合。 通过嵌入导电元件，可以使导电元件更小，并且在导电元件和模塑料之间存在间隙。 可以通过将连接器的最大宽度添加空间余量来确定连接器的间距。 另一个封装上的各种类型的触点可以结合到导电元件上。

公开(公告)号：US20120217632A1

公开(公告)日：2012-08-30

申请号：US13035586

申请日：2011-02-25

申请人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

发明人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

IPC分类号： H01L23/498

CPC分类号： H01L24/16 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.

摘要翻译： 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。

公开(公告)号：US20110057313A1

公开(公告)日：2011-03-10

申请号：US12899168

申请日：2010-10-06

申请人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

发明人： Kuo-Chin Chang ,  Han-Ping Pu ,  Pei-Haw Tsao

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.

摘要翻译： 描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。 当焊球焊接到柱上时，引脚被封装在焊料材料内。 引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。 此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。

公开(公告)号：US07855443B2

公开(公告)日：2010-12-21

申请号：US11732853

申请日：2007-04-04

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。