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    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
    64.
    发明授权
    Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners 有权
    具有裂纹停止区域的半导体芯片，用于减少从芯片边缘/角落的裂纹扩展

    公开(公告)号：US07875502B2

    公开(公告)日：2011-01-25

    申请号：US12788521

    申请日：2010-05-27

    申请人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    发明人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC分类号： H01L21/78

    CPC分类号： H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    摘要： A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

    摘要翻译： 芯片制造方法。 提供的结构包括：半导体衬底上的晶体管，半导体衬底上的N个互连层和晶体管（N> 0），以及N个互连层上的第一介电层。 晶体管电耦合到N个互连层。 在第一介电层（P，Q> 0）上形成有P断裂区域和Q裂纹停止区域。 第一电介质层夹在N互连层和形成在第一介电层上的第二电介质层之间。 每个P裂纹停止区域被第一和第二介电层完全包围。 第二电介质层夹在第一电介质层和形成在第二电介质层上的底部填充层之间。 每个Q裂纹停止区域被第一介电层和底部填充层完全包围。

    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS
    66.
    发明申请
    SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS 有权
    带切割停止区域的半导体焊盘，用于减少芯片边缘/角落的裂纹传播

    公开(公告)号：US20100233872A1

    公开(公告)日：2010-09-16

    申请号：US12788521

    申请日：2010-05-27

    申请人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    发明人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

    IPC分类号： H01L21/71

    CPC分类号： H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

    摘要： A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

    摘要翻译： 芯片制造方法。 提供的结构包括：半导体衬底上的晶体管，半导体衬底上的N个互连层和晶体管（N> 0），以及N个互连层上的第一介电层。 晶体管电耦合到N个互连层。 在第一介电层（P，Q> 0）上形成有P断裂区域和Q裂纹停止区域。 第一电介质层夹在N互连层和形成在第一介电层上的第二电介质层之间。 每个P裂纹停止区域被第一和第二介电层完全包围。 第二电介质层夹在第一电介质层和形成在第二电介质层上的底部填充层之间。 每个Q裂纹停止区域被第一介电层和底部填充层完全包围。

    SEMICONDUCTOR PACKAGE HAVING NON-ALIGNED ACTIVE VIAS
    70.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING NON-ALIGNED ACTIVE VIAS 有权
    具有非对准活性VIAS的半导体封装

    公开(公告)号：US20080054482A1

    公开(公告)日：2008-03-06

    申请号：US11469950

    申请日：2006-09-05

    申请人： Jean Audet ,  Luc Guerin ,  David L. Questad ,  David J. Russell

    发明人： Jean Audet ,  Luc Guerin ,  David L. Questad ,  David J. Russell

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A semiconductor package is disclosed including a first capture pad isolated from an adjacent second capture pad by an insulator; a first plurality of electrically active vias connecting the first capture pad to the second capture pad; a third capture pad isolated from the second capture pad by an insulator; and a second plurality of electrically active vias connecting the second capture pad to the third capture pad. Each via of the first plurality of active vias is non-aligned with each via of the second plurality of active vias. The structure provides reduction of strain on the vias when a shear force is applied to a ball grid array used therewith while minimizing the degradation of the electrical signals.

    摘要翻译： 公开了一种半导体封装，其包括通过绝缘体与相邻的第二捕获垫隔离的第一捕获垫; 将第一捕获垫连接到第二捕获垫的第一多个电活动通孔; 通过绝缘体与第二捕获垫隔离的第三捕获垫; 以及将第二捕获垫连接到第三捕获垫的第二多个电活动通孔。 第一多个有源通孔的每个通孔与第二多个有源通孔的每个通孔不对齐。 当将剪切力施加到与其一起使用的球栅阵列同时最小化电信号的劣化时，该结构提供通孔上的应变减小。