公开(公告)号：US20160293433A1

公开(公告)日：2016-10-06

申请号：US14674127

申请日：2015-03-31

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu

IPC: H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/0271 ,  H01L21/266 ,  H01L21/3086

Abstract: Some embodiments include a method of fabricating features associated with a semiconductor substrate. A first region of the semiconductor substrate is altered relative to a second region. The altered first region has different physisorption characteristics for polynucleotide relative to the second region. The altered first region and the second region are exposed to polynucleotide. The polynucleotide selectively adheres to either the altered first region or the second region to form a polynucleotide mask. The polynucleotide mask is used during fabrication of features associated with the semiconductor substrate.

Abstract translation: 一些实施例包括制造与半导体衬底相关联的特征的方法。 半导体衬底的第一区域相对于第二区域改变。 改变的第一区域对于多核苷酸相对于第二区域具有不同的物理吸附特性。 改变的第一区域和第二区域暴露于多核苷酸。 多核苷酸选择性地粘附到改变的第一区域或第二区域以形成多核苷酸掩模。 在制造与半导体衬底相关的特征时使用多核苷酸掩模。

公开(公告)号：US20160293406A1

公开(公告)日：2016-10-06

申请号：US14677445

申请日：2015-04-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/02

CPC classification number: H01L21/02118 ,  B82Y40/00 ,  H01L21/02227 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31138 ,  H01L29/02 ,  H01L29/0665 ,  H01L29/66007

Abstract: A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.

Abstract translation: 形成纳米结构的方法包括在图案化的衬底上形成核酸结构的定向自组装。 图案化衬底包括多个区域。 图案化衬底上的每个区域被特别地定制成用于在定向自组装中吸附特定的核酸结构。

公开(公告)号：US09397187B2

公开(公告)日：2016-07-19

申请号：US14543349

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L21/28 ,  H01L21/44 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/872 ,  H01L45/00 ,  H01L49/02

CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

公开(公告)号：US09356145B2

公开(公告)日：2016-05-31

申请号：US14456435

申请日：2014-08-11

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S257/90

Abstract: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.

Abstract translation: 在集成电路中使用应变栅电极导致晶体管具有改善的载流子迁移率，改进的驱动特性和减少的源极漏极结泄漏。 栅电极应变可以通过不对称放置应力诱导结构作为栅电极的一部分获得。

公开(公告)号：US09349945B2

公开(公告)日：2016-05-24

申请号：US14516347

申请日：2014-10-16

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L27/222 ,  H01L27/226 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. The depletion of the magnetic material enables crystallization of the depleted magnetic material through crystal structure propagation from a neighboring crystalline material, without interference from the now-enriched getter seed region. This promotes high tunnel magnetoresistance and high magnetic anisotropy strength. Also during formation, another diffusive species is transferred from a precursor oxide material to the getter seed region, due to a chemical affinity elicited by another getter species. The depletion of the oxide material enables lower electrical resistance and low damping in the cell structure. Methods of fabrication and semiconductor devices are also disclosed.

Abstract translation: 磁性电池包括磁性，二次氧化物和吸气剂种子区域。 在形成期间，由于吸气剂物质引起的化学亲和力，扩散物质从前体磁性材料转移到吸气剂种子区域。 磁性材料的耗尽使得耗尽的磁性材料能够通过晶体结构从邻近的结晶材料传播而结晶，而不会受到现在富集的吸气剂种子区域的干扰。 这促进了高隧道磁阻和高磁各向异性强度。 在形成期间，由于由另一吸气剂物质引起的化学亲和力，另外的扩散物质从前体氧化物材料转移到吸气剂种子区域。 氧化物材料的耗尽使电池结构中的电阻降低和阻尼减小。 还公开了制造方法和半导体器件。

公开(公告)号：US09343677B2

公开(公告)日：2016-05-17

申请号：US14596666

申请日：2015-01-14

Applicant: Micron Technology, Inc.

Inventor： John A. Smythe, III ,  Gurtej S. Sandhu

IPC: G11C11/34 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/165 ,  G11C13/0007 ,  G11C2213/56 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1683

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

公开(公告)号：US09337210B2

公开(公告)日：2016-05-10

申请号：US13964309

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

Abstract translation: 垂直铁电场效应晶体管结构包括隔离芯。 过渡金属二硫属元素材料环绕隔离芯并具有1个单层至7个单层的侧壁厚度。 铁电栅极电介质材料围绕过渡金属二硫属元素材料。 导电栅极材料围绕铁电栅极电介质材料。 过渡金属二硫属元素材料在导电栅极材料的高度向内和向外向外延伸。 导电接触件直接抵靠过渡金属二硫属化物材料的侧向外侧壁，其是导电栅极材料的顶部向内，或b）导电栅极材料的向外侧。 公开了其他实施例。

公开(公告)号：US09331275B2

公开(公告)日：2016-05-03

申请号：US14253989

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: G11C13/00 ,  H01L45/00

CPC classification number: H01L45/1253 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0016 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/52 ,  G11C2213/53 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state.

公开(公告)号：US09330932B1

公开(公告)日：2016-05-03

申请号：US14674302

申请日：2015-03-31

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu

IPC: H01L21/02 ,  H01L21/308 ,  H01L21/70

CPC classification number: H01L21/702 ,  H01L21/02112 ,  H01L21/02359 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086

Abstract: Some embodiments include a method in which a mixture of polynucleotide structures comprises a set of surface shapes. Surface shapes of some polynucleotide structures are complementary to surface shapes of other polynucleotide structures. The complementary surface shapes lock together along interfaces between adjacent polynucleotide structures to incorporate the polynucleotide structures into a polynucleotide mask. The polynucleotide mask is used during fabrication of features associated with a semiconductor substrate. Some embodiments include a method in which a semiconductor substrate comprises registration regions configured to adhere individual polynucleotide structures to specific locations of the semiconductor substrate. The adhered polynucleotide structures are incorporated into a polynucleotide mask which is used during fabrication of features associated with the semiconductor substrate.

Abstract translation: 一些实施方案包括多核苷酸结构的混合物包含一组表面形状的方法。 一些多核苷酸结构的表面形状与其他多核苷酸结构的表面形状互补。 互补表面形状沿相邻多核苷酸结构之间的界面锁定在一起，以将多核苷酸结构并入多核苷酸掩模。 在制造与半导体衬底相关的特征时使用多核苷酸掩模。 一些实施例包括其中半导体衬底包括被配置成将单个多晶核苷酸结构粘附到半导体衬底的特定位置的配准区域的方法。 将粘附的多核苷酸结构并入到在与半导体衬底相关联的特征的制造期间使用的多核苷酸掩模中。

公开(公告)号：US20160118402A1

公开(公告)日：2016-04-28

申请号：US14987613

申请日：2016-01-04

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/8239 ,  H01L27/0738 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/42328 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

Abstract translation: 一些实施例包括形成半导体结构的方法。 可以形成n型掺杂材料和p型掺杂材料的交替层。 交替层可以被图案化成通过开口彼此间隔开的多个垂直柱。 开口可以衬有隧道电介质，电荷储存材料和阻挡电介质。 绝缘材料和导电控制栅极材料的交替层可以形成在衬里的开口内。 一些实施例包括形成NAND单元电池的方法。 可以形成交替的n型材料和p型材料的柱。 柱可以衬有隧道电介质层，电荷存储材料层和阻挡电介质层。 可以在排列的柱之间形成绝缘材料和导电控制栅极材料的交替层。 一些实施例包括半导体结构，并且一些实施例包括NAND单元单元。