公开(公告)号：US20140319679A1

公开(公告)日：2014-10-30

申请号：US14326789

申请日：2014-07-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/48 ,  H01L23/28 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L23/28 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805 ,  H01L2924/00012

Abstract: A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Abstract translation: 半导体器件具有带有裸片附着区域的载体。 半导体管芯安装到具有与载体相对的后表面的管芯附着区域。 模块化互连单元安装在载体上并且围绕半导体管芯周围或周围区域安装，使得模块化互连单元偏离半导体管芯的后表面。 密封剂沉积在载体，半导体管芯和模块化互连单元上。 去除密封剂的第一部分以暴露半导体管芯，并且移除第二部分以露出模块化互连单元。 载体被移除。 在半导体管芯和模块化互连单元上形成互连结构。 模块化互连单元包括通过半导体器件的垂直互连结构或凸块。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。

公开(公告)号：US20140246779A1

公开(公告)日：2014-09-04

申请号：US14274599

申请日：2014-05-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US20140159251A1

公开(公告)日：2014-06-12

申请号：US14038575

申请日：2013-09-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Pandi C. Marimuthu ,  Il Kwon Shim ,  Yaojian Lin ,  Won Kyoung Choi

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/568 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias.

Abstract translation: 半导体器件包括半导体管芯。 第一互连结构设置在半导体管芯的外围区域上。 半导体元件设置在半导体管芯上。 半导体部件包括第二互连结构。 半导体部件设置在半导体管芯上方，以将第二互连结构与第一互连结构对准。 第一互连结构包括设置在半导体管芯的第一和第二相邻侧面周围的多个互连单元，以形成围绕半导体管芯的互连单元的L形边界。 在垂直于第一互连结构的半导体管芯上形成第三互连结构。 在半导体管芯和第一互连结构之上形成绝缘层。 通过绝缘层形成多个通孔，并且通过第二互连结构设置在通孔内形成第一互连结构。

公开(公告)号：US20140091482A1

公开(公告)日：2014-04-03

申请号：US13832809

申请日：2013-03-15

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Heinz-Peter Wirtz ,  Seung Wook Yoon ,  Pandi C. Marimuthu

IPC: H01L23/28 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L21/565 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Abstract translation: 半导体器件具有包括多个半导体管芯的半导体晶片。 在半导体晶片上形成绝缘层。 通过LDA去除绝缘层的一部分以暴露半导体管芯的有效表面的一部分。 第一导电层形成在半导体管芯的有源表面上的接触焊盘上。 单个半导体晶片以分离半导体管芯。 半导体管芯设置在载体上，半导体管芯的有源表面与载体偏移。 在半导体管芯和载体上沉积密封剂以覆盖半导体管芯的一侧和有源表面的暴露部分。 在第一导电层上形成互连结构。 或者，MUF材料沉积在半导体管芯的一侧和有源表面的暴露部分上。

公开(公告)号：US20140091455A1

公开(公告)日：2014-04-03

申请号：US14097534

申请日：2013-12-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Thomas J. Strothmann ,  Damien M. Pricolo ,  Il Kwon Shim ,  Yaojioan Lin ,  Heinz-Peter Wirtz ,  Seung Wook Yoon ,  Pandi C. Marimuthu

IPC: H01L21/78 ,  H01L23/522 ,  H01L23/28

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L24/12 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/951 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

Abstract translation: 半导体器件具有固定尺寸的载体。 从第一半导体晶片切割多个第一半导体管芯。 第一半导体管芯设置在载体上。 载体上的第一半导体管芯的数量与从第一半导体晶片分离的第一半导体管芯的尺寸和数量无关。 在第一半导体管芯和载体上并围绕第一半导体管芯和载体沉积密封剂以形成重构的板。 在重构的面板上形成互连结构，同时留下没有互连结构的密封剂。 重建的面板通过密封剂分离。 从载体上去除第一半导体管芯。 具有与第一半导体管芯的尺寸不同的尺寸的第二半导体管芯设置在载体上。 载体的固定尺寸与第二半导体管芯的尺寸无关。

公开(公告)号：US20130285236A1

公开(公告)日：2013-10-31

申请号：US13933406

申请日：2013-07-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Pandi C. Marimuthu ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/302 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/10125 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/1301 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/11849 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

Abstract translation: 半导体器件在衬底的第一表面中具有导电通孔。 在衬底的第一表面上形成第一互连结构。 在第一互连结构上形成第一凸点。 第一凸起形成在导电通孔上方或偏离导电通孔。 密封剂沉积在第一凸起和第一互连结构之上。 去除一部分密封剂以露出第一凸块。 去除衬底的第二表面的一部分以暴露导电通孔。 密封剂提供结构支撑，并且在使衬底变薄时不需要单独的载体晶片。 第二互连结构形成在衬底的第二表面上。 在第一凸起上形成第二凸点。 多个半导体器件可以通过导电通孔堆叠并电连接。

公开(公告)号：US20130228917A1

公开(公告)日：2013-09-05

申请号：US13772683

申请日：2013-02-21

Applicant: STATS CHIPPAC, LTD.

Inventor： Seung Wook Yoon ,  Jose A. Caparas ,  Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/311 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76804 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Abstract translation: 半导体器件具有沉积在半导体管芯上方和周围的具有密封剂的半导体管芯。 在密封剂的第一表面上形成互连结构。 开口由密封剂的第二表面形成到密封剂的第一表面以暴露互连结构的表面。 凸起凹陷形成在开口内并设置在互连结构的表面上。 提供半导体封装。 半导体封装设置在密封剂的第二表面上并电连接到凸块。 多个互连结构形成在半导体封装上，以将半导体封装电连接到凸块。 半导体封装包括存储器件。 半导体器件包括高度小于1毫米的半导体器件。 开口包括通过激光直接消融形成的锥形侧壁。