公开(公告)号：US12040293B2

公开(公告)日：2024-07-16

申请号：US18055241

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/532 ,  H01L21/02 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L24/05 ,  H01L21/02068 ,  H01L24/03 ,  H01L2224/02321 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/035 ,  H01L2224/0391 ,  H01L2224/05008 ,  H01L2224/05083 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05188 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/04953 ,  H01L2924/0535 ,  H01L2924/05994

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US12009322B2

公开(公告)日：2024-06-11

申请号：US17670481

申请日：2022-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan Tai ,  Ting-Ting Kuo ,  Yu-Chih Huang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Chih-Hua Chen ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L23/3128 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/12105

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US11961791B2

公开(公告)日：2024-04-16

申请号：US17663970

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC: H01L23/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L25/105 ,  H01L24/16 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US11901319B2

公开(公告)日：2024-02-13

申请号：US17233967

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Min Huang ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L21/481 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/07 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L21/568 ,  H01L23/49827 ,  H01L2224/0239 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/18162 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/27

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

公开(公告)号：US20230343133A1

公开(公告)日：2023-10-26

申请号：US18343036

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chih-Hua Chen ,  Yu-Jen Cheng ,  Chih-Wei Lin ,  Yu-Feng Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: G06V40/13 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: G06V40/1329 ,  H01L21/561 ,  H01L23/49827 ,  H01L24/19 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/16227 ,  H01L2224/83005 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81911 ,  H01L2224/85005 ,  H01L2224/18

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

公开(公告)号：US11664287B2

公开(公告)日：2023-05-30

申请号：US17201445

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Chih-Wei Lin ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768 ,  H01L21/82 ,  H01L23/04 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L21/82 ,  H01L23/04 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/73 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48096 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/48465 ,  H01L2224/48095 ,  H01L2924/00

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.

公开(公告)号：US11584019B2

公开(公告)日：2023-02-21

申请号：US17114178

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Ti Wang ,  Chih-Wei Lin ,  Fu-Hsien Li ,  Yi-Ming Chen ,  Cheng-Ho Hung

IPC: B25J11/00 ,  G01B11/30 ,  H01L21/67 ,  H01L21/02 ,  H01L21/66 ,  B25J18/00 ,  G01B11/24 ,  G01N33/00 ,  H01L21/673 ,  H01L21/677 ,  B23P6/00 ,  B25J1/04

Abstract: An apparatus for semiconductor manufacturing includes an input port to receive a carrier, wherein the carrier includes a carrier body, a housing installed onto the carrier body, and a filter installed between the carrier body and the housing. The apparatus further includes a first robotic arm to uninstall the housing from the carrier and to reinstall the housing into the carrier; one or more second robotic arms to remove the filter from the carrier and to install a new filter into the carrier; and an output port to release the carrier to production.

公开(公告)号：US11446851B2

公开(公告)日：2022-09-20

申请号：US16398164

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Feng Weng ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Yao-Tong Lai ,  Chia-Min Lin

IPC: B29C45/03 ,  B29C45/14 ,  H01L21/56 ,  B29C45/00

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

公开(公告)号：US11322421B2

公开(公告)日：2022-05-03

申请号：US16924208

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Yen Chang ,  Chih-Wei Lin ,  Hao-Yi Tsai ,  Kuo-Lung Pan ,  Chun-Cheng Lin ,  Tin-Hao Kuo ,  Yu-Chia Lai ,  Chih-Hsuan Tai

IPC: H01L23/40 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.

公开(公告)号：US20220130794A1

公开(公告)日：2022-04-28

申请号：US17646816

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Jui Huang ,  Chien Ling Hwang ,  Chih-Wei Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.