公开(公告)号：US20110067235A1

公开(公告)日：2011-03-24

申请号：US12805753

申请日：2010-08-18

申请人： Deepak Keshav Pai ,  Chris H. Simon

发明人： Deepak Keshav Pai ,  Chris H. Simon

IPC分类号： H01K3/10

CPC分类号： H05K3/423 ,  H05K3/0094 ,  H05K3/427 ,  H05K2201/09563 ,  H05K2203/1394 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.

摘要翻译： 本发明包括用于填充印刷线路板中的孔和通过这些方法制造的印刷线路板的方法。 所述方法包括在印刷线路板的孔内镀金属导体，同时保护印刷线路板的导电表面不被光致抗蚀剂膜电镀。 印刷电路板的侧表面被光致抗蚀剂覆盖。 光致抗蚀剂暴露于显影光，除了覆盖板的一侧上的孔的光致抗蚀剂被遮蔽以防止孔暴露于显影光。 去除了覆盖孔的未显影光致抗蚀剂。 对该板进行电镀工艺，其中将导电材料沉积在孔中，但是在该板的导电表面上的光致抗蚀剂防止导电材料被电镀在该板的表面上。

公开(公告)号：US07892441B2

公开(公告)日：2011-02-22

申请号：US11806598

申请日：2007-06-01

申请人： Deepak K. Pai

发明人： Deepak K. Pai

IPC分类号： H01B13/00 ,  H01K3/10

CPC分类号： H05K3/4007 ,  H01L21/486 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/113 ,  H05K2201/0394 ,  H05K2201/09881 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of manufacturing an interposer is provided, including the steps of providing a sheet with a copper layer and polyimide layer, laser drilling holes in the polyimide layer down to the copper layer, filling the holes with copper and extending the copper above the polyimide layer to define caps, removing portions of the copper layer to form conductive pads, and filling gaps between the conductive pads with an insulator, wherein individual conductive pads are in electrical contact with corresponding individual caps.

摘要翻译： 提供一种制造插入件的方法，包括以下步骤：提供具有铜层和聚酰亚胺层的片材，在聚酰亚胺层中的铜层下方的激光钻孔，用铜填充孔并将铜延伸到聚酰亚胺层上方 以限定帽，去除铜层的部分以形成导电焊盘，以及用绝缘体填充导电焊盘之间的间隙，其中各个导电焊盘与相应的单独盖电接触。

公开(公告)号：US07856710B2

公开(公告)日：2010-12-28

申请号：US11964355

申请日：2007-12-26

申请人： Takashi Kariya ,  Akira Mochida

发明人： Takashi Kariya ,  Akira Mochida

IPC分类号： H01K3/10

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/0353 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of manufacturing a printed wiring board including preparing a high-dielectric capacitor sheet including a ceramic high-dielectric layer sandwiched by upper and lower electrode sheets, attaching the high-dielectric capacitor sheet to a first insulating layer, forming through holes for the upper and lower electrode sheets such that the through holes penetrate through the ceramic high-dielectric layer and upper and lower electrode sheets, forming a second insulating layer which fills the through holes and covers an upper surface of the high-dielectric capacitor sheet, forming an upper electrode connecting first hole, an upper electrode connecting second hole and a lower electrode connecting hole, filling the upper holes with conductive material such that the upper electrode connecting first hole and the upper electrode connecting second hole are connected to form an upper electrode connection portion, and filling the lower electrode connecting hole with conductive material to form a lower electrode connecting portion.

摘要翻译： 一种印刷电路板的制造方法，其特征在于，包括：制作包含由上下电极片夹着的陶瓷高电介质层的高介电电容器片，将所述高介电电容片贴附在第一绝缘层上， 和下电极片，使得通孔穿过陶瓷高介电层和上下电极片，形成填充通孔并覆盖高介电电容器片的上表面的第二绝缘层，形成上电极片 电极连接第一孔，上电极连接第二孔和下电极连接孔，用导电材料填充上孔，使得连接第一孔和连接第二孔的上电极的上电极连接形成上电极连接部， 并用导电材料填充下电极连接孔 m为下部电极连接部。

公开(公告)号：US07752752B1

公开(公告)日：2010-07-13

申请号：US11621402

申请日：2007-01-09

申请人： Sukianto Rusli ,  Ronald Patrick Huemoeller

发明人： Sukianto Rusli ,  Ronald Patrick Huemoeller

IPC分类号： H01K3/10

CPC分类号： H05K3/045 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/107 ,  H05K2203/0723 ,  Y10T29/49165 ,  Y10T29/49167

摘要： A method of fabricating a substrate includes forming a first conductive layer on a dielectric layer, forming a resist layer on the first conductive layer, and forming laser-ablated artifacts through the first resist layer, through the first conductive layer, and at least partially into the dielectric layer. A second conductive layer is formed within the laser-ablated artifacts. The laser-ablated artifacts are filled to form an overfilled circuit pattern. The resist layer and the first conductive layer are removed. Further, a portion of the overfilled circuit pattern is removed to form an embedded circuit pattern embedded within the dielectric layer.

摘要翻译： 一种制造衬底的方法包括在电介质层上形成第一导电层，在第一导电层上形成抗蚀剂层，并通过第一导电层，通过第一抗蚀剂层形成激光烧蚀的假象，并至少部分地形成 电介质层。 在激光烧蚀的伪像内形成第二导电层。 激光烧蚀的人造物被填充以形成过满的电路图案。 去除抗蚀剂层和第一导电层。 此外，过充电电路图案的一部分被去除以形成嵌入电介质层内的嵌入电路图案。

公开(公告)号：US07752751B2

公开(公告)日：2010-07-13

申请号：US12058912

申请日：2008-03-31

申请人： Christopher James Kapusta ,  Donald Cunningham ,  Richard Joseph Saia

发明人： Christopher James Kapusta ,  Donald Cunningham ,  Richard Joseph Saia

IPC分类号： H01K3/10

CPC分类号： H05K9/0039 ,  C23C14/046 ,  H01L23/29 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K3/284 ,  H05K2201/0129 ,  H05K2201/0133 ,  H05K2201/09872 ,  H05K2203/1311 ,  H05K2203/1361 ,  H05K2203/1366 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A system and method for providing shielding to an electrical system is disclosed. A conformal shield is formed by applying a conformal insulating coating to an electrical system. A plurality of openings are formed in the insulating coating at desired locations and a first metallic layer is deposited over the insulating coating and in each of the plurality of openings, the first metallic layer being electrically connected with the circuit board at the desired locations. A second metallic layer is then deposited onto the first metallic layer to increase a thickness of the metallic layers.

摘要翻译： 公开了一种用于向电气系统提供屏蔽的系统和方法。 通过将适形绝缘涂层施加到电气系统来形成保形屏蔽。 在绝缘涂层中在所需位置处形成多个开口，并且第一金属层沉积在绝缘涂层上方，并且在多个开口中的每一个中，第一金属层在所需位置处与电路板电连接。 然后将第二金属层沉积到第一金属层上以增加金属层的厚度。

公开(公告)号：US07748115B2

公开(公告)日：2010-07-06

申请号：US11777988

申请日：2007-07-13

申请人： Sunappan Vasudivan ,  Chee Wai Lu ,  Boon Keng Lok

发明人： Sunappan Vasudivan ,  Chee Wai Lu ,  Boon Keng Lok

IPC分类号： H01K3/10 ,  H05K7/00

CPC分类号： H05K1/186 ,  H05K1/0231 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

摘要： A method of forming a circuit board, the method comprising mounting at least one passive component on a first surface of a first laminate material; interconnecting the passive component to contact traces and vias of the first laminate material; and attaching a second laminate material to the first surface of the first laminate material utilizing a lamination process, the second laminate material sheet having at least one of a recess, a through-hole or both formed therein for accommodating the passive component in the second laminate.

摘要翻译： 一种形成电路板的方法，所述方法包括在第一层压材料的第一表面上安装至少一个无源部件; 将所述被动部件与所述第一层压材料的接触迹线和通孔相互连接; 并且利用层压工艺将第二层压材料附着到第一层压材料的第一表面上，第二层压材料板具有形成在其中的凹部，通孔或两者中的至少一个，用于容纳第二层压体中的被动部件 。

公开(公告)号：US20100167561A1

公开(公告)日：2010-07-01

申请号：US12653035

申请日：2009-12-07

申请人： Dirk Dewar Brown ,  John David Williams ,  William B. Long

发明人： Dirk Dewar Brown ,  John David Williams ,  William B. Long

IPC分类号： H01R12/00 ,  H01K3/10

CPC分类号： H05K7/1069 ,  H01L23/32 ,  H01L24/72 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01R12/52 ,  H01R12/714 ,  H01R13/03 ,  H01R13/2407 ,  H01R43/007 ,  H01R43/205 ,  H05K3/326 ,  H05K3/4092 ,  Y10T29/49165 ,  H01L2924/00

摘要： An elastic contact array circuitized substrate includes a circuitized substrate provided with circuit traces, and an array of three dimensional contact elements joined to the circuitized substrate and electrically coupled to the circuit traces. In one configuration, the array of three dimensional contacts are formed in a spring sheet material having anisotropic grains whose long direction is selected with respect to the longitudinal direction of elastic contact arms, in accordance with desired properties. In another configuration of the invention, the circuit traces are formed integrally within the spring sheet material.

摘要翻译： 弹性接触阵列电路化衬底包括设置有电路迹线的电路化衬底和连接到电路化衬底并电耦合到电路迹线的三维接触元件的阵列。 在一种结构中，根据所需的性质，三维触点阵列形成为具有相对于弹性接触臂的纵向方向选择长方向的各向异性颗粒的弹簧片材料。 在本发明的另一种结构中，电路迹线一体形成在弹簧片材料内。

公开(公告)号：US20100071951A1

公开(公告)日：2010-03-25

申请号：US12067408

申请日：2006-08-14

申请人： Tokuo Yoshida ,  Akiyoshi Fujii ,  Tatsuya Fujita

发明人： Tokuo Yoshida ,  Akiyoshi Fujii ,  Tatsuya Fujita

IPC分类号： H05K1/11 ,  H01K3/10

CPC分类号： H05K3/4069 ,  H05K1/115 ,  H05K3/125 ,  H05K3/1258 ,  H05K3/4664 ,  H05K2201/09727 ,  H05K2201/09854 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165

摘要： The multilayer wiring board is provided with a lower layer wiring (8), and an upper layer wiring (10) formed on the lower layer wiring (8) through an interlayer insulating layer (9). On the interlayer insulating layer (9), a contact hole (11) is provided for interconnecting the upper layer wiring (8) with the lower layer wiring (10). A region surrounded by an inner wall (13) which forms the contact hole (11) is permitted to have a linewidth region wherein a wide line region (13A) and protruding regions (13B, 13C) as regions having different linewidths are connected. Thus, film thickness distribution of an ink baked product (12) formed at the contact hole (11) rises at the protruding regions (13B, 13C), and highly reliable multilayer interconnection can be performed between the lower layer wiring (8) and the upper layer wiring (10).

摘要翻译： 多层布线基板具有下层布线（8）和通过层间绝缘层（9）形成在下层布线（8）上的上层布线（10）。 在层间绝缘层（9）上设置有用于使上层布线（8）与下层布线（10）互连的接触孔（11）。 由形成接触孔（11）的内壁（13）包围的区域被允许具有作为具有不同线宽的区域的宽线区域（13A）和突出区域（13B，13C）的线宽区域。 因此，形成在接触孔（11）处的油墨烘烤产品（12）的膜厚分布在突出区域（13B，13C）处上升，并且可以在下层布线（8）和 上层布线（10）。

公开(公告)号：US07673387B2

公开(公告)日：2010-03-09

申请号：US11659190

申请日：2005-08-04

申请人： Risto Tuominen ,  Petteri Palm

发明人： Risto Tuominen ,  Petteri Palm

IPC分类号： H01K3/10 ,  H01L21/00

CPC分类号： H01L24/82 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H05K1/188 ,  H05K3/4652 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for manufacturing a circuit-board layer on a base surface (2), which base surface (2) includes conductor patterns (19). The circuit-board layer being manufactured comprises a conductor-pattern layer (14), an insulating layer (1), and at least one component (6) inside the insulating-material layer (1). According to the invention, the component (6) is attached to the conductor layer (4), the conductor layer (4) is aligned relative to the base surface (2) attached with the aid of an insulating material (1) to the base surface (2). An insulating-material layer (1) is thus formed between the conductor layer (4) and the base surface (2), on which the said at least one component (6) is located. Electrical contacts are formed between the contact areas (7) of the component (6) and the conductor layer (4), in such a way that contact openings (17) are opened at the positions of the contact areas (7) of the component (6) and conductive material is made in the contact openings (17). The conductor layer (4) is patterned to form a conductor-pattern layer (14), and at least one via (20) is made between the conductor-pattern layer (14) and the conductor patterns (19) of the base surface (2).

摘要翻译： 一种用于在基底表面（2）上制造电路板层的方法，该基底表面（2）包括导体图案（19）。 正在制造的电路板层包括导体图案层（14），绝缘层（1）和绝缘材料层（1）内的至少一个部件（6）。 根据本发明，组件（6）附接到导体层（4），导体层（4）相对于借助于绝缘材料（1）附接到基座的基座表面（2）对准到底座 表面（2）。 因此，在所述至少一个部件（6）所在的导体层（4）和基底表面（2）之间形成绝缘材料层（1）。 在部件（6）的接触区域（7）和导体层（4）之间形成电触点，使得接触开口（17）在部件的接触区域（7）的位置处被打开 （6），并且在所述接触开口（17）中形成导电材料。 导体层（4）被图形化以形成导体图案层（14），并且在导体图案层（14）和基底表面的导体图案（19）之间形成至少一个通孔（20） 2）。

公开(公告)号：US07669321B1

公开(公告)日：2010-03-02

申请号：US11375435

申请日：2006-03-14

申请人： John Benjamin Levy ,  John Martin ,  Farhad Pakravan

发明人： John Benjamin Levy ,  John Martin ,  Farhad Pakravan

IPC分类号： H01K3/10

CPC分类号： H05K1/0268 ,  H05K3/0047 ,  H05K3/429 ,  H05K2203/0207 ,  H05K2203/175 ,  Y10T29/49117 ,  Y10T29/49165 ,  Y10T29/49718 ,  Y10T29/49726 ,  Y10T29/49764 ,  Y10T408/03 ,  Y10T408/173 ,  Y10T408/175

摘要： A test site is incorporated on a circuit board having a set of test connections passing through a test via on respective test connection layer, the test connection layers including (1) a first layer adjacent to a target layer, and (2) a second layer spaced apart from the target layer with the first layer therebetween. The test via is back-drilled from the direction of the second layer to remove undesired via metallization, breaking the test connections of all the layers through which it passes, and the continuity of the test connections is measured to determine a pattern of broken and non-broken test connections resulting from the back-drilling. The pattern of broken and non-broken test connections is examined to ascertain the actual depth of the back-drilling in relation to the target layer.

摘要翻译： 测试点被并入在具有通过相应测试连接层上的测试通路的一组测试连接的电路板上，测试连接层包括（1）与目标层相邻的第一层，和（2）第二层 与目标层间隔开，其间具有第一层。 测试通孔从第二层的方向回溯，以消除不期望的通孔金属化，破坏其通过的所有层的测试连接，并测量测试连接的连续性，以确定断裂和非断裂的图案 - 由后钻造成的连续测试连接。 检查断裂和未断裂的测试连接的模式，以确定相对于目标层的后钻的实际深度。