公开(公告)号：US09691696B2

公开(公告)日：2017-06-27

申请号：US15005220

申请日：2016-01-25

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/288 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/04 ,  H01L23/14 ,  H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 620.3) connect the dies to the cavity's bottom wall (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

公开(公告)号：US09666560B1

公开(公告)日：2017-05-30

申请号：US14951892

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Guilian Gao ,  Hong Shen ,  Rajesh Katkar ,  Belgacem Haba

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L25/0655 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/116 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2224/81 ,  H01L2224/83

Abstract: A microelectronic assembly includes a dielectric element having bumps projecting from a first surface thereof, the bumps having end surfaces flush with a planarized encapsulation. A circuit structure having a thickness less than or equal to 10 microns, formed by depositing two or more dielectric layers and conductive layers on the respective dielectric layers, has electrically conductive features thereon which electrically contact the bumps. The circuit structure can be formed separately on a carrier and then joined with the bumps on the dielectric element, or the circuit structure can be formed by a build up process on the planarized surface of the encapsulation and the planarized surfaces of the bumps.

公开(公告)号：US09502347B2

公开(公告)日：2016-11-22

申请号：US14629271

申请日：2015-02-23

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Arkalgud R. Sitaram

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/09 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08168 ,  H01L2224/08501 ,  H01L2224/73204 ,  H01L2224/80487 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1304 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

Abstract translation: 两个微电子部件（110,120），例如 模具和插入件彼此结合。 部件的接触焊盘（110C）中的一个包括金属，另一部件具有与金属反应形成金属硅化物（504）的硅（410）。 然后通过其中一个部件制成一个孔（510），以到达金属硅化物，甚至可能连接另一部件的未反应的金属（110C）。 该孔填充有可能是金属的导体（130），以提供可电耦合到可附接到其它电路元件或微电子部件的接触焊盘（120C.B）的导电通孔，例如。 到印刷电路板。

公开(公告)号：US09402312B2

公开(公告)日：2016-07-26

申请号：US14275741

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Zhuowen Sun ,  Charles G. Woychik ,  Arkalgud Sitaram

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H05K1/11 ,  H01L25/00 ,  H05K1/18 ,  H05K1/02 ,  H05K1/14

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1615 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/141 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract translation: 组合插入器（120）包括多个成分插入件（120.i），每个具有其自己的衬底（120.iS）并且在衬底的顶部和/或底部上具有电路层（例如再分配层）。 顶层电路层可以是可以互连不同插入件的公共电路层（120R.T）的一部分。 类似地，底部电路层可​​以是公共电路层（120R.B）的一部分。 成分插入器基板（120.iS）最初是公共晶片的一部分，并且在将成分插入器基板与晶片分离之前制造公共顶层电路层。 与使用单个大型基材相比，分离的基材的使用降低了应力。 还提供其他功能。

公开(公告)号：US09324626B2

公开(公告)日：2016-04-26

申请号：US14558462

申请日：2014-12-02

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/31 ,  H01L21/288 ,  H01L21/56 ,  H01L21/768 ,  H01L23/04 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 623) connect the dies to the cavity's bottom all (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

Abstract translation: 堆叠的管芯（110）通过由可模制材料形成的多个密封层（524）封装在插入件的空腔（304）中。 导电路径（520,623）将模具连接到空腔的底部（304B），并且通过穿过底壁的TSV连接到插入件下方的导体。 导电路径可以形成为各自形成在各个密封层中的通孔（514）中的段。 每个段可以通过电镀形成在下段上; 电镀电流可以通过TSV和较早形成的片段从插入件的下方提供。 还提供其他功能。

公开(公告)号：US20160049383A1

公开(公告)日：2016-02-18

申请号：US14532806

申请日：2014-11-04

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Hong Shen ,  Christopher W. Lattin ,  Guilian Gao ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/11003 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/185 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Abstract translation: 一种用于集成器件的器件和方法包括：第一再分配层，其包括一个或多个第一导体，一个或多个第一裸片，其安装到第一再分布层的第一表面并电耦合到第一导体，一个或多个第一柱具有第一导体 末端附接到第一模具和与第一端相对的第二端，一个或多个第二柱，其具有附接到第一再分布层的第一表面的第三端和与第三端相对的第四端，以及包括一个或多个第二端的第二再分布层 导体，第二再分布层附接到第一柱的第二端和第二柱的第四端。 在一些实施例中，集成装置还包括安装到第一再分配层的第二表面的散热器。 第二表面与第一表面相对。

公开(公告)号：US09252127B1

公开(公告)日：2016-02-02

申请号：US14328380

申请日：2014-07-10

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/538 ,  H01L21/98 ,  H01L21/50 ,  H01L21/67 ,  H01L25/065 ,  H01L23/00 ,  H01L21/52

CPC classification number: H01L25/0652 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/8182 ,  H01L2224/85205 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract translation: 半导体集成电路（110）或组件至少部分地设置在两个插入件（120）之间的空腔中。 导电通孔（204M）通过至少一个插入件或至少穿过插入器的衬底，并到达半导体集成电路或组件。 其他导电通孔（204M.1）至少部分地通过多个插入件并且连接到到达或者电容耦合到半导体IC或组件的导电通孔。 还提供其他功能。

公开(公告)号：US09165793B1

公开(公告)日：2015-10-20

申请号：US14268899

申请日：2014-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/00 ,  H01L21/56

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Abstract translation: 制造集成电路封装的方法包括提供具有限定空腔的第一区域的处理晶片。 在第一区域形成电容器。 电容器具有一对电极，每对电极耦合到一对导电焊盘中的一个，其至少一个设置在处理晶片的下表面上。 还提供了具有上表面的插入件，其具有导电焊盘和设置在其上的至少一个半导体管芯。 芯片具有与内插器的再分配层（RDL）电导耦合的集成电路。 把手晶片的下表面被结合到插入件的上表面，使得模具设置在空腔的下方或内部，并且处理晶片的导电焊盘以金属间隔结合到插入件的导电焊盘上， 金属键。

公开(公告)号：US20150262928A1

公开(公告)日：2015-09-17

申请号：US14558462

申请日：2014-12-02

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/288 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 623) connect the dies to the cavity's bottom all (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

Abstract translation: 堆叠的管芯（110）通过由可模制材料形成的多个密封层（524）封装在插入件的空腔（304）中。 导电路径（520,623）将模具连接到空腔的底部（304B），并且通过穿过底壁的TSV连接到插入件下方的导体。 导电路径可以形成为各自形成在各个密封层中的通孔（514）中的段。 每个段可以通过电镀形成在下段上; 电镀电流可以通过TSV和较早形成的片段从插入件的下方提供。 还提供其他功能。