公开(公告)号：US06897571B2

公开(公告)日：2005-05-24

申请号：US10263319

申请日：2002-10-01

申请人： Salman Akram ,  Derek J. Gochnour ,  Michael E. Hess ,  David R. Hembree

发明人： Salman Akram ,  Derek J. Gochnour ,  Michael E. Hess ,  David R. Hembree

IPC分类号： B23P17/00 ,  B26D3/00 ,  B28D1/32 ,  B28D5/02 ,  H01L21/00 ,  H01L21/301 ,  H01L23/58 ,  H01L29/00 ,  H05K3/02 ,  H05K3/20 ,  H05K3/30

CPC分类号： H01L21/67092 ,  B28D5/024 ,  B28D5/029 ,  Y10T83/0222 ,  Y10T83/0363 ,  Y10T83/04 ,  Y10T83/0524 ,  Y10T83/7726 ,  Y10T83/7809 ,  Y10T83/7868

摘要： A semiconductor wafer saw and method of using the same for dicing semiconductor wafers including a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

摘要翻译： 半导体晶片锯及其使用方法，用于切割包括具有可变侧向分度能力的晶片锯和多个叶片的半导体晶片。 晶片锯由于其可变的分度能力，可将其上具有多个不同尺寸的半导体器件的晶片切割成其各自的分立元件。 此外，具有多个叶片的晶片锯，其中一些可相对于其它叶片独立地横向或垂直移动，可以更有效地将硅晶片切割成单独的半导体器件。

公开(公告)号：US20050098888A1

公开(公告)日：2005-05-12

申请号：US11015586

申请日：2004-12-17

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/495 ,  H01L23/52

CPC分类号： H01L24/85 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L24/86 ,  H01L2224/02166 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48666 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48766 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/85375 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/48781 ,  H01L2224/48681 ,  H01L2224/29099

摘要： A wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

摘要翻译： 与半导体器件的接合焊盘和引线框架的引线之间的引线键合或TAB带的改进的导体引线与半导体器件的接合焊盘接合。 更具体地，改进的引线键合，其中半导体器件的表面上的接合焊盘包括铜层和至少一层金属和/或至少在铜层和一层金属之间的材料的阻挡层的层 铜层形成接合垫。

公开(公告)号：US20050093557A1

公开(公告)日：2005-05-05

申请号：US11011420

申请日：2004-12-13

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： G01R1/04 ,  G01R31/26

CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  H01L21/4846 ,  H01L23/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05644 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed layer over the insulation layer; depositing a metal layer over the seed layer; and etching contact members from the seed and metal layers using a single mask step. In a preferred embodiment, the metal layer is coated with another metal layer that matches the metal of the packaged part's electrical communication nodes. In one embodiment, the contact surfaces of the silicon contact are plated in gold and are planar. Included within the scope of the current invention are at least one method of testing an LGA package and at least one method of allowing electrical communication with a packaged part.

公开(公告)号：US06884706B2

公开(公告)日：2005-04-26

申请号：US10371145

申请日：2003-02-20

申请人： Leonard Forbes ,  Kie Y. Ahn ,  Salman Akram

发明人： Leonard Forbes ,  Kie Y. Ahn ,  Salman Akram

IPC分类号： H01L21/44 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L27/148 ,  H01L29/768

CPC分类号： H01L23/5225 ,  H01L23/53209 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01105 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include permalloy and/or Ni45Fe55 films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.

公开(公告)号：US06882167B2

公开(公告)日：2005-04-19

申请号：US10423124

申请日：2003-04-25

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： G01R1/04 ,  G01R31/26 ,  G01R31/02

CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  H01L21/4846 ,  H01L23/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05644 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a test system, a silicon interconnect is provided that can accommodate a packaged part, such as a Land Grid Array (LGA) package. The interconnect can be made by etching a silicon substrate to form projections therefrom; forming an insulation or passivation layer through deposition or growth; depositing a seed layer over the insulation layer; depositing a metal layer over the seed layer; and etching contact members from the seed and metal layers using a single mask step. In a preferred embodiment, the metal layer is coated with another metal layer that matches the metal of the packaged part's electrical communication nodes. In one embodiment, the contact surfaces of the silicon contact are plated in gold and are planar. Included within the scope of the current invention are at least one method of testing an LGA package and at least one method of allowing electrical communication with a packaged part.

摘要翻译： 在测试系统中，提供了可以容纳诸如陆地网格阵列（LGA）封装的封装部件的硅互连。 可以通过蚀刻硅衬底以形成突起来进行互连; 通过沉积或生长形成绝缘或钝化层; 在绝缘层上沉积种子层; 在种子层上沉积金属层; 以及使用单个掩模步骤从种子和金属层蚀刻接触构件。 在优选实施例中，金属层涂覆有与包装部分的电通信节点的金属匹配的另一金属层。 在一个实施例中，硅接触的接触表面镀金并且是平面的。 包括在本发明的范围内的是至少一种测试LGA封装的方法和允许与封装部件进行电气通信的至少一种方法。

公开(公告)号：US20050042856A1

公开(公告)日：2005-02-24

申请号：US10931374

申请日：2004-08-31

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： G01R1/04 ,  H01L21/68 ,  H01L21/44

CPC分类号： H01L21/6835 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y50/00 ,  B33Y70/00 ,  B33Y80/00 ,  G01R1/0483 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/05599

摘要： A method for protecting intermediate conductive elements, such as bond wires, of semiconductor device assemblies includes selectively altering a state of substantially unconsolidated material adjacent to an intermediate conductive element. Selective alteration of the state of the substantially unconsolidated material may be effected by way of a programmed material consolidation process, such as stereolithography. Programmed material consolidation may be accompanied by a feature-recognition technique, such as machine vision. When a programmed material consolidation process is effected, a plurality of adjacent, mutually adhered regions, such as layers, of a protective structure may be formed.

摘要翻译： 用于保护半导体器件组件的中间导电元件（例如接合线）的方法包括选择性地改变与中间导电元件相邻的基本上未固结的材料的状态。 基本上未固化的材料的状态的选择性改变可以通过程序材料固结方法如立体光刻来实现。 程序化材料整合可能伴随着特征识别技术，如机器视觉。 当进行编程材料固结处理时，可以形成保护结构的多个相邻的相互粘合的区域，例如层。

公开(公告)号：US06853210B1

公开(公告)日：2005-02-08

申请号：US10198895

申请日：2002-07-18

申请人： Warren M. Farnworth ,  Salman Akram

发明人： Warren M. Farnworth ,  Salman Akram

IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  H05K3/32 ,  G01R31/26

CPC分类号： G01R1/0466 ,  G01R1/06738 ,  G01R1/07314 ,  G01R1/07378 ,  G01R3/00 ,  H05K3/326 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a support member over the recess configured to electrically engage a bumped contact. The support member is suspended over the recess on spiral leads formed on a surface of the substrate. The spiral leads allow the support member to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the spiral leads twist the support member relative to the bumped contact to facilitate penetration of oxide layers thereon. The spiral leads can be formed by attaching a polymer substrate with the leads thereon to the substrate, or by forming a patterned metal layer on the substrate. In an alternate embodiment contact, the support member is suspended over the surface of the substrate on raised spring segment leads.

摘要翻译： 用于测试半导体部件的互连件包括基板和基板上的触点，用于与部件上的凸起触点进行临时电连接。 每个接触件包括凹部和位于所述凹部上方的支撑构件，所述支撑构件被构造成电接合凸起的触点。 支撑构件悬挂在形成在基板的表面上的螺旋形引线上的凹部上。 螺旋引线允许支撑构件在凹部内沿z方向移动以适应凸起接触件的高度和平面度的变化。 此外，螺旋引线相对于凸起接触扭转支撑构件，以便于其上的氧化物层的穿透。 可以通过将聚合物基板与其上的引线附接到基板上，或者通过在基板上形成图案化的金属层来形成螺旋引线。 在替代实施例的接触中，支撑构件悬挂在衬底的凸起的弹簧段引线的表面上。

公开(公告)号：US20050020094A1

公开(公告)日：2005-01-27

申请号：US10623788

申请日：2003-07-21

申请人： Leonard Forbes ,  Joseph Geusic ,  Salman Akram

发明人： Leonard Forbes ,  Joseph Geusic ,  Salman Akram

IPC分类号： H01L21/469 ,  H01L21/762

CPC分类号： H01L21/76254

摘要： One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

摘要翻译： 本公开的一个方面涉及一种用应变半导体形成晶片的方法。 在该方法的各种实施例中，在半导体膜和衬底晶片之一上形成预定轮廓。 将半导体膜结合到基板晶片上，并且将预定轮廓拉直以在半导体膜中引起预定应变。 在各种实施例中，衬底晶片弯曲到弯曲位置，当衬底晶片处于弯曲位置时，衬底晶片的一部分结合到半导体层，并且衬底晶片被松弛以在半导体中引起预定应变 层。 本文提供了其它方面和实施例。

公开(公告)号：US20050017327A1

公开(公告)日：2005-01-27

申请号：US10914331

申请日：2004-08-09

申请人： Leonard Forbes ,  Kie Ahn ,  Salman Akram

发明人： Leonard Forbes ,  Kie Ahn ,  Salman Akram

IPC分类号： G11C7/18 ,  H01L23/522 ,  H01P5/12

CPC分类号： G11C7/02 ,  G11C7/18 ,  H01L23/5225 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The transmission line circuit includes forming a second layer of electrically conductive material on the second layer of insulating material.

摘要翻译： 传输线电路提供用于改进集成电路上的传输线操作的结构。 传输线电路在衬底上包括第一层导电材料。 第一层绝缘材料形成在导电材料的第一层上。 在第一绝缘材料层上形成多个高磁导率金属线。 高渗透性金属线的数量包括复合六铁氧体膜。 多个传输线形成在绝缘材料的第一层上并且与多个高导磁率金属线之间并且平行。 在传输线和高磁导率金属线上形成第二层绝缘材料。 传输线电路包括在第二绝缘材料层上形成第二层导电材料。

公开(公告)号：US06847110B2

公开(公告)日：2005-01-25

申请号：US10366190

申请日：2003-02-12

申请人： Salman Akram ,  Alan G. Wood

发明人： Salman Akram ,  Alan G. Wood

IPC分类号： H01L21/60 ,  H01L23/373 ,  H01L23/10

CPC分类号： H01L23/291 ,  H01L23/3114 ,  H01L23/3732 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/83851 ,  H01L2924/00 ,  H01L2924/013

摘要： A method and apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein, is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond layer and to electrically communicate with the semiconductor device. The heat produced from the semiconductor device and thermally conducting through the conductive pads is thermally conducted to the heat sink or diamond layer and away from the interconnections, i.e., solder bump connections, between a semiconductor device and a carrier substrate in a flip-chip assembly. As a result, thermal fatigue is substantially prevented in a flip-chip assembly.