公开(公告)号：US20070122635A1

公开(公告)日：2007-05-31

申请号：US11619612

申请日：2007-01-04

申请人： Su-Tsai Lu ,  Shu-Ming Chang ,  Shyh-Ming Chang ,  Yao-Sheng Lin ,  Yuan-Chang Huang

发明人： Su-Tsai Lu ,  Shu-Ming Chang ,  Shyh-Ming Chang ,  Yao-Sheng Lin ,  Yuan-Chang Huang

IPC分类号： B32B13/04

CPC分类号： B32B15/08 ,  B32B7/12 ,  B32B9/005 ,  B32B15/20 ,  B32B27/281 ,  B32B27/283 ,  B32B2457/08 ,  B32B2457/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  Y10T428/24917 ,  Y10T428/31667 ,  H01L2924/00014 ,  H01L2924/00

摘要： A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.

摘要翻译： 提供具有缓冲层的接合结构及其形成方法。 接合结构包括其上具有金属焊盘的第一衬底，覆盖在衬底表面上的保护层，形成在金属焊盘上的第一粘合金属层，涂覆在保护层上的缓冲层和金属焊盘，第一金属 覆盖在缓冲层上的第二基板和其上具有电极和接合层的第二基板。 第一金属层，电极和接合层被接合以形成接合结构。 可以通过表面活化或热压直接粘合。 该方法使用较少的步骤并且更可靠。 粘结结构所需的温度较低。 接触表面之间的结合密度增加到细间距。 增加接合点的质量，因为产生了接触表面之间的较少的污染物。

公开(公告)号：US06998718B2

公开(公告)日：2006-02-14

申请号：US10765961

申请日：2004-01-29

申请人： Shu-Ming Chang ,  Lee-Cheng Shen

发明人： Shu-Ming Chang ,  Lee-Cheng Shen

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the PCB will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

摘要翻译： 公开了晶片级芯片级封装结构及其制造方法，以使用正常的半导体工艺在凸块下方形成牺牲层。 该凸块用于连接Si晶圆和PCB之间的信号。 牺牲层和PCB之间的界面是整个结构中最薄弱的部分。 当施加到凸块的应力过载时，牺牲层和PCB之间的界面将崩溃，以消除由Si晶片和PCB的不同热膨胀系数产生的应力。 牺牲层将有助于避免碰撞发生的碰撞以保护Si晶片和PCB之间的电导通。

公开(公告)号：US20060027908A1

公开(公告)日：2006-02-09

申请号：US11074732

申请日：2005-03-09

申请人： Shu-Ming Chang ,  Tzong-Che Ho

发明人： Shu-Ming Chang ,  Tzong-Che Ho

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

摘要： A 3-D stackable semiconductor package includes a first component and a second component. The semiconductor package is formed by stacking the back of the first component and the back of the second component together. The metal pads on the surfaces of the first component and the second component are redistributed to the edge of the first and the second components by a redistribution layer. A plurality of electric conduction posts is formed at the edge of the first and the second component to transmit electric signals between them. The semiconductor package transmits electric signals to the PCB by the electric conductive bumps.

公开(公告)号：US5417105A

公开(公告)日：1995-05-23

申请号：US198245

申请日：1994-02-18

申请人： Erasmo Martinez ,  Steven E. Walmsley ,  Shu-Ming Chang

发明人： Erasmo Martinez ,  Steven E. Walmsley ,  Shu-Ming Chang

IPC分类号： G01M3/20 ,  G01N1/24 ,  G01M3/04

CPC分类号： G01N1/24 ,  G01M3/205 ,  G01N2001/242

摘要： A leak detection system (50) including a flow accelerator for directing and accelerating leaking gas toward a sampling probe (70). A probe input tube (72) is inserted into one end (62B) of a larger diameter adapter tube (60) to position the end of the tube (72) past a suction opening (62D). The other end (62A) of the adapter tube is positioned to receive leaking gas. A suction is applied to the suction opening, which tends to draw the leaking gas into the adapter tube end (62A). Some of the leaking gas is drawn into the suction opening, and some into the end of the sampling tube. The suction causes the leaking gas to be accelerated toward the sampling probe input port. The suction can be created by a venturi (66C) through which is passed a gas under pressure. The acceleration of the gas through the venturi creates the suction. The flow accelerator significantly reduces the time required to locate small gas leaks.

摘要翻译： 一种泄漏检测系统（50），包括用于将泄漏的气体引导并加速到采样探针（70）的流动加速器。 探针输入管（72）插入到较大直径的适配器管（60）的一端（62B）中，以将管（72）的端部定位通过吸入口（62D）。 适配器管的另一端（62A）定位成接收泄漏气体。 吸入口被抽吸到吸入口，吸入口容易将泄漏的气体吸入适配器管端部（62A）。 一些泄漏的气体被吸入吸入口，有些泄漏气体进入采样管的末端。 抽吸会使泄漏的气体朝向采样探头输入端口加速。 抽吸可以由文丘里管（66C）产生，通过压力通过气体。 通过文氏管的气体加速产生吸力。 流量加速器显着缩短了定位小气体泄漏所需的时间。

公开(公告)号：US08673686B2

公开(公告)日：2014-03-18

申请号：US13492649

申请日：2012-06-08

申请人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L21/44

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定多个器件区域的多个预定划线的第一衬底; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环，位于芯片支撑环的周边的切割支撑结构，围绕 所述芯片支撑环分别具有将所述止动环与所述切割支撑结构和所述芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US08536672B2

公开(公告)日：2013-09-17

申请号：US13050949

申请日：2011-03-18

申请人： Shu-Ming Chang ,  Tien-Hao Huang

发明人： Shu-Ming Chang ,  Tien-Hao Huang

IPC分类号： H01L23/48 ,  H01L31/02

CPC分类号： H01L27/14636 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/552 ,  H01L23/562 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/3512 ,  H01L2924/00

摘要： An image sensor package includes an image sensor die having an active side and a backside, wherein an image sensor device region and a bond pad are provided on the active side. A through-silicon-via (TSV) structure extending through the thickness of the image sensor die is provided to electrically connect the bond pad. A multi-layer re-distributed interconnection structure is provided on the backside of the image sensor die. A solder mask or passivation layer covers the multi-layer re-distributed interconnection structure.

摘要翻译： 图像传感器封装包括具有有源侧和背面的图像传感器芯片，其中在活动侧上设置有图像传感器装置区域和接合焊盘。 提供延伸穿过图像传感器管芯的厚度的贯通硅通孔（TSV）结构以电连接接合焊盘。 在图像传感器芯片的背面设置多层重新分配的互连结构。 焊接掩模或钝化层覆盖多层再分布互连结构。

公开(公告)号：US08409925B2

公开(公告)日：2013-04-02

申请号：US13178375

申请日：2011-07-07

申请人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L21/00

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

公开(公告)号：US08367477B2

公开(公告)日：2013-02-05

申请号：US12722486

申请日：2010-03-11

申请人： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

发明人： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC分类号： H01L23/48

CPC分类号： B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

摘要： An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

公开(公告)号：US20120313261A1

公开(公告)日：2012-12-13

申请号：US13492649

申请日：2012-06-08

申请人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

摘要： An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defining a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively, a cutting support structure located on peripheries of the chip support rings, a plurality of stop rings surrounding the chip support rings respectively, wherein a gap pattern separating the stop rings from the cutting support structure and the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

摘要翻译： 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定多个器件区域的多个预定划线的第一衬底; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环，位于芯片支撑环的周边的切割支撑结构，围绕 所述芯片支撑环分别具有将所述止动环与所述切割支撑结构和所述芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US08310050B2

公开(公告)日：2012-11-13

申请号：US13024902

申请日：2011-02-10

申请人： Wei-Ming Chen ,  Shu-Ming Chang

发明人： Wei-Ming Chen ,  Shu-Ming Chang

IPC分类号： H01L23/48

CPC分类号： H01L23/49811 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24246 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/83

摘要： A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

摘要翻译： 公开了一种芯片封装。 封装包括载体衬底，至少两个半导体芯片，填充材料层，保护层和多个导电凸块。 载体基板包括接地区域。 半导体芯片设置在载体基板的接地区域上。 每个半导体芯片包括至少一个信号焊盘，并且包括电连接到接地区域的至少一个接地焊盘。 填充材料层形成在载体衬底上并覆盖半导体芯片。 保护层覆盖填充层。 多个导电凸块设置在保护层的上方并与半导体芯片电连接。 还公开了芯片封装的制造方法。