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    Depletion-Free MOS using Atomic-Layer Doping
    83.
    发明申请
    Depletion-Free MOS using Atomic-Layer Doping 有权
    消耗MOS的原子层掺杂

    公开(公告)号：US20100068873A1

    公开(公告)日：2010-03-18

    申请号：US12211546

    申请日：2008-09-16

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L21/22

    CPC classification number: H01L21/823842 ,  H01L21/2254 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/6659

    Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

    Abstract translation: 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。

    Diffusion barrier for damascene structures
    85.
    发明申请
    Diffusion barrier for damascene structures 审中-公开
    镶嵌结构的扩散屏障

    公开(公告)号：US20060099802A1

    公开(公告)日：2006-05-11

    申请号：US10985149

    申请日：2004-11-10

    Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

    Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

    IPC: H01L21/4763

    CPC classification number: H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

    Abstract: A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed. Thereafter, one or more barrier layers may be formed and the via may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by performing, for example, a plasma process in an argon environment.

    Abstract translation: 提供了具有形成在电介质层中的通孔的半导体结构。 沿着通孔的侧壁的电介质材料的暴露的孔部分或完全密封。 此后，可以形成一个或多个阻挡层，并且可以用导电材料填充通孔。 形成在密封层之上的阻挡层表现出更连续的阻挡层。 通过在氩气环境中进行例如等离子体处理，可以将孔部分或完全密封。

    Barrier structure for semiconductor devices
    86.
    发明申请
    Barrier structure for semiconductor devices 审中-公开
    半导体器件的阻挡结构

    公开(公告)号：US20050266679A1

    公开(公告)日：2005-12-01

    申请号：US10995752

    申请日：2004-11-23

    Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

    Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/52

    CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76865

    Abstract: A via having a unique barrier layer structure is provided. In an embodiment, a via is formed by forming a barrier layer in a via. The barrier layer along the bottom of the via is partially or completely removed, and the via is filled with a conductive material. In another embodiment, a first barrier layer is formed along the bottom and sidewalls of the via. Thereafter, the first barrier layer along the bottom of the via is partially or completely removed, and a second barrier layer is formed.

    Abstract translation: 提供具有独特的阻挡层结构的通孔。 在一个实施例中，通孔在通孔中形成阻挡层而形成通孔。 沿着通孔底部的阻挡层被部分地或完全去除，并且通孔用导电材料填充。 在另一个实施例中，沿着通孔的底部和侧壁形成第一阻挡层。 此后，沿通孔底部的第一阻挡层被部分地或完全地去除，形成第二阻挡层。

    Method of forming multilayer diffusion barrier for copper interconnections
    89.
    发明申请
    Method of forming multilayer diffusion barrier for copper interconnections 有权
    形成铜互连多层扩散阻挡层的方法

    公开(公告)号：US20050051512A1

    公开(公告)日：2005-03-10

    申请号：US10942355

    申请日：2004-09-16

    Applicant: Jing-Cheng Lin

    Inventor： Jing-Cheng Lin

    IPC: H01L21/768 ,  H01B13/00

    CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

    Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层通过沉积氮化钨底层，随后形成SiH4 / NH3或SiH4 / H2浸泡形成WSiN层，并沉积钨的最终顶层形成。 本发明用于在逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

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