公开(公告)号：US09607862B2

公开(公告)日：2017-03-28

申请号：US13610262

申请日：2012-09-11

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

摘要： Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

公开(公告)号：US20140077383A1

公开(公告)日：2014-03-20

申请号：US13615960

申请日：2012-09-14

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/585 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

摘要： A structure and method of making an offset-trench crackstop, which forms an air gap in a passivation layer that is adjacent to a passivated top metal layer of a metal crackstop in an integrated circuit (IC) die. The offset-trench crackstop may expose a portion of a topmost dielectric layer in the crackstop region, not expose a topmost patterned metal layer of the metal crackstop, and may be interposed between the metal crackstop and an active device region. Alternatively, the offset-trench crackstop may expose a portion of the topmost dielectric layer, which separates an outermost metal layer and an innermost metal layer of the metal crackstop, and does not expose any of the topmost patterned metal layer of the metal crackstop, where the innermost metal layer of the metal crackstop is interposed between the offset-trench crackstop in the crackstop region and the active device region of the IC die.

摘要翻译： 一种制造偏移沟槽裂缝挡板的结构和方法，其在与集成电路（IC）模具中的金属裂缝挡板的钝化顶部金属层相邻的钝化层中形成气隙。 偏移沟槽裂缝挡板可能暴露裂纹区域中最顶层电介质层的一部分，而不会暴露金属裂缝挡板的最顶层图案化的金属层，并且可以插入在金属裂缝挡板和有源器件区域之间。 或者，偏移沟槽裂缝挡板可以暴露最外层介电层的一部分，其分隔金属裂纹器的最外金属层和最内金属层，并且不暴露金属裂纹器的任何最顶层的图案化金属层，其中 金属裂缝挡板的最内侧金属层介于裂纹区域的偏移沟槽裂缝和IC模具的有源器件区域之间。

公开(公告)号：US20140070401A1

公开(公告)日：2014-03-13

申请号：US13610262

申请日：2012-09-11

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L21/306 ,  H01L23/498

CPC分类号： H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

摘要： Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

摘要翻译： 各种实施方案包括形成互连结构的方法以及通过这些方法形成的结构。 在一个实施例中，一种方法可以包括：提供具有：光敏聚酰亚胺（PSPI）层的前体互连结构; 一个控制崩溃芯片连接（C4）凸起覆盖PSPI层; 以及覆盖C4凸块并且接触C4凸块的一侧的焊料。 该方法还可以包括使与C4凸起相邻的PSPI层的一部分凹陷以在C4凸起下形成PSPI基座。 该方法还可以包括形成邻接PSPI基座和C4凸块的底部填充物，其中底部填充物和焊料形成与PSPI基座分离的界面。

公开(公告)号：US20140021600A1

公开(公告)日：2014-01-23

申请号：US13553882

申请日：2012-07-20

申请人： Timothy H. Daubenspeck ,  Brian M. Erwin ,  Jeffrey P. Gambino ,  Wolfgang Sauter ,  George J. Scott

发明人： Timothy H. Daubenspeck ,  Brian M. Erwin ,  Jeffrey P. Gambino ,  Wolfgang Sauter ,  George J. Scott

IPC分类号： H01L23/488 ,  H01L21/768

CPC分类号： H01L23/3192 ,  H01L23/525 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/0614 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/14104 ,  H01L2224/14131 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.

摘要翻译： 公开了一种集成电路（IC）芯片，其包括在后端（BEOL）层中的多个金属垂直互连访问（通孔），BEOL层上的再分配层（RDL），BEOL层具有多个键 焊盘，每个接合焊盘通过RDL连接到至少一个对应的金属通孔; 以及连接到每个接合焊盘的焊料凸块，其中每个焊料凸块横向偏离连接到所述接合焊盘的相应金属通孔朝向所述IC芯片的中心偏移距离，其中所述偏移距离在所述IC 芯片。 在一个实施例中，每个焊料凸块的偏移距离与IC芯片的中心与该焊料凸块的相应焊料凸块焊盘结构的中心之间的距离成比例。

公开(公告)号：US08629557B2

公开(公告)日：2014-01-14

申请号：US13414877

申请日：2012-03-08

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/48 ,  H01L21/00 ,  B23K31/00

CPC分类号： H01L22/30 ,  H01L22/12 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2924/01029

摘要： Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

摘要翻译： 用于检测基座侧壁焊料润湿的结构和方法。 该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及 在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱 在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。

公开(公告)号：US20130234316A1

公开(公告)日：2013-09-12

申请号：US13415902

申请日：2012-03-09

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/05 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

摘要： The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

摘要翻译： 本发明提供一种半导体芯片结构，其具有在铝焊盘结构下方的至少一个铝焊盘结构和聚酰亚胺缓冲层，其中聚酰亚胺缓冲层与铝焊盘结构自对准，以及其形成方法。 该方法包括在基板上形成聚酰亚胺缓冲层，在缓冲层上形成铝焊盘结构，并且使用铝焊盘结构作为掩模，蚀刻基板以除去铝以外的其他处理的基板 垫结构。

公开(公告)号：US08476762B2

公开(公告)日：2013-07-02

申请号：US13463879

申请日：2012-05-04

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/061 ,  H01L2224/0613 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

摘要翻译： 用于半导体芯片封装的具有球限制冶金（BLM）结构的无铅控制崩溃芯片连接（C4）的结构和方法，其在芯片级后端（BEOL）工艺中减少芯片级开裂， 加入冷却。 在芯片连接冷却期间受到拉伸应力的BLM结构的边缘被保护以防止金属种子层的底切，由芯片的湿法蚀刻引起，以通过电镀从芯片的表面和焊料回流中去除金属层 阻挡层，其覆盖金属种子层的相应边缘。

公开(公告)号：US08426247B2

公开(公告)日：2013-04-23

申请号：US13463855

申请日：2012-05-04

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L21/44

CPC分类号： H01L23/49816 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/11822 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/17051 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars.

摘要翻译： 将芯片与芯片载体，陶瓷封装等（封装基板）连接的方法比半导体芯片表面上的通常的第一焊球和聚合物柱形成的小，并且将粘合剂施加到聚合物柱的远端。 该方法还形成与芯片将附接到的封装衬底的相应表面上尺寸相似的第二焊球。 然后，该方法将半导体芯片的表面定位在封装衬底的相应表面的旁边。 粘合剂将聚合物柱的末端粘合到包装基底的相应表面上。 该方法加热第一焊球和第二焊球以将第一焊球和第二焊球接合成焊料柱。

公开(公告)号：US08350383B2

公开(公告)日：2013-01-08

申请号：US12503870

申请日：2009-07-16

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/04

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof.

摘要翻译： 在一个实施例中，IC芯片封装可以包括IC芯片，其包括包括延伸超过IC芯片的侧壁的突出部分的上表面，以及围绕侧壁和突出部分下方的底部填充材料。 悬垂防止底部填充材料在IC芯片的上表面上延伸。 在另一个实施例中，首先将球栅阵列（BGA）安装到两个连接的IC芯片封装的较低的焊盘上。 由于BGA首先形成在下部IC芯片封装上，所以BGA用作其上的底部填充材料的坝。 底部填充材料围绕相应的IC芯片延伸并围绕BGA的多个焊料元件的底部以及其各自的着陆焊盘的至少一部分。

公开(公告)号：US20120217636A1

公开(公告)日：2012-08-30

申请号：US13463879

申请日：2012-05-04

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/061 ,  H01L2224/0613 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

摘要翻译： 用于半导体芯片封装的具有球限制冶金（BLM）结构的无铅控制崩溃芯片连接（C4）的结构和方法，其在芯片级后端（BEOL）工艺中减少芯片级开裂， 加入冷却。 在芯片连接冷却期间受到拉伸应力的BLM结构的边缘被保护以防止金属种子层的底切，由芯片的湿法蚀刻引起，以通过电镀从芯片的表面和焊料回流中去除金属层 阻挡层，其覆盖金属种子层的相应边缘。